公开(公告)号：US20120319282A1

公开(公告)日：2012-12-20

申请号：US13164448

申请日：2011-06-20

Applicant: Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Belgacem Haba ,  Craig Mitchell

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/1094 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。 在一些实施例中，异种材料可以是导电材料或纳米合金。 互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

公开(公告)号：US07476304B2

公开(公告)日：2009-01-13

申请号：US10947628

申请日：2004-09-21

Applicant: Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

Inventor： Jalal Ashjaee ,  Boguslaw Nagorski ,  Bulent M. Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC: C25D17/00 ,  C25D5/00

CPC classification number: C25F7/00 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885

Abstract: Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and the electrical contact, and the workpiece is moved with respect to the anode and the electrical contact. Full-face electroplating or electropolishing over the workpiece frontal side surface, in its entirety, is thus permitted.

Abstract translation: 通过提供具有正面与工件正面的阳极区域并将工件正面与至少一个电气电连接的阳极进行导电材料沉积在导电材料上或从半导体工件的工件正面去除导电材料 通过将电触点和工件正面推入彼此靠近，在阳极区域外部接触。 在阳极和电接触之间施加电位，并且工件相对于阳极和电触点移动。 因此允许在工件正面侧面上进行全面电镀或电解抛光。

公开(公告)号：US07309413B2

公开(公告)日：2007-12-18

申请号：US10459321

申请日：2003-06-10

Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

IPC: C25D5/04 ,  C25D7/12 ,  C25F3/12

CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

Abstract translation: 可以通过包括第一和第二导电元件的特定装置来提供导电材料在包含导电材料的电解质的衬底的包括半导体晶片的表面上的基本均匀沉积。 第一导电元件可以具有相同或不同构造的多个电触点，或者可以是导电焊盘的形式，并且可以在基本上所有的衬底表面上与衬底表面接触或以其他方式电互连。 当在电解质与衬底表面和第二导电元件物理接触的同时在第一和第二导电元件之间施加电势时，导电材料沉积在衬底表面上。 可以使施加在阳极和阴极之间的电压的极性反转，从而可以对沉积的导电材料进行电蚀刻。

公开(公告)号：US07201829B2

公开(公告)日：2007-04-10

申请号：US09960236

申请日：2001-09-20

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Jeff A. Bogart

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Jeff A. Bogart

IPC: C25F3/16 ,  C25F5/00 ,  C25D17/00

CPC classification number: H01L21/76879 ,  B24B37/042 ,  C25D5/02 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D17/001 ,  C25F7/00 ,  H01L21/2885

Abstract: The present invention includes a mask plate design that includes at least one or a plurality of channels portions on a surface of the mask plate, into which electrolyte solution will accumulate when the mask plate surface is disposed on a surface of wafer, and out of which the electrolyte solution will freely flow. There are also at least one or a plurality of polish portions on the mask plate surface that allow for polishing of the wafer when the mask plate surface is disposed on a surface of wafer.

Abstract translation: 本发明包括掩模板设计，其包括在掩模板的表面上的至少一个或多个通道部分，当掩模板表面设置在晶片的表面上时，电解质溶液将积聚在其中，并且其中 电解液会自由流动。 掩模板表面上还有至少一个或多个抛光部分，当掩模板表面设置在晶片的表面上时，允许抛光晶片。

公开(公告)号：US20060017169A1

公开(公告)日：2006-01-26

申请号：US11168559

申请日：2005-06-29

Applicant: Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

Inventor： Panayotis Andricacos ,  Hariklia Deligianni ,  John Dukovic ,  Daniel Edelstein ,  Wilma Horkans ,  Chao-Kun Hu ,  Jeffrey Hurd ,  Kenneth Rodbell ,  Cyprian Uzoh ,  Kwong-Hon Wong

IPC: H01L23/48 ,  H01L21/44

CPC classification number: C25D3/38 ,  C25D5/022 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76885

Abstract: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract translation: 描述了用于集成电路芯片的亚微米互连结构的制造的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US20050034976A1

公开(公告)日：2005-02-17

申请号：US10946703

申请日：2004-09-21

Applicant: Homayoun Talieh ,  Cyprian Uzoh

Inventor： Homayoun Talieh ,  Cyprian Uzoh

IPC: B24B37/16 ,  C25D5/06 ,  C25D5/22 ,  C25D7/12 ,  C25D17/00 ,  C25D17/12 ,  C25D17/14 ,  C25F7/00 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  C25D5/48

CPC classification number: B24B37/16 ,  C25D5/06 ,  C25D5/22 ,  C25D7/123 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/3212

Abstract: The present invention provides a method and apparatus that plates/deposits a conductive material on a semiconductor substrate and then polishes the same substrate. This is achieved by providing multiple chambers in a single apparatus, where one chamber can be used for plating/depositing the conductive material and another chamber can be used for polishing the semiconductor substrate. The plating/depositing process can be performed using brush plating or electro chemical mechanical deposition and the polishing process can be performed using electropolishing or chemical mechanical polishing. The present invention further provides a method and apparatus for intermittently applying the conductive material to the semiconductor substrate and also intermittently polishing the substrate when such conductive material is not being applied to the substrate. Furthermore, the present invention provides a method and apparatus that plates/deposits and/or polishes a conductive material and improves the electrolyte mass transfer properties on a substrate using a novel anode assembly.

Abstract translation: 本发明提供一种在半导体衬底上沉积/沉积导电材料然后抛光相同衬底的方法和装置。 这通过在单个设备中提供多个室来实现，其中一个室可以用于电镀/沉积导电材料，并且另一个室可以用于抛光半导体衬底。 电镀/沉积工艺可以使用刷镀或电化学机械沉积进行，并且可以使用电抛光或化学机械抛光进行抛光工艺。 本发明还提供一种用于将导电材料间歇地施加到半导体衬底的方法和装置，并且当这种导电材料未被施加到衬底时也间歇地抛光衬底。 此外，本发明提供了一种使用新型阳极组件对导电材料进行平板/沉积和/或抛光并改善基板上的电解质传质性质的方法和装置。

公开(公告)号：US06852630B2

公开(公告)日：2005-02-08

申请号：US09841622

申请日：2001-04-23

Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Halit N. Yakupoglu ,  Homayoun Talieh

Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Halit N. Yakupoglu ,  Homayoun Talieh

IPC: B23H5/08 ,  C25F3/14 ,  H01L21/288 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/32115 ,  B23H5/08 ,  C25F3/14 ,  H01L21/2885 ,  H01L21/32134 ,  H01L21/7684

Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.

Abstract translation: 用于可选地沉积或蚀刻晶片层的系统包括与晶片相对的掩模板，掩模板具有将溶液输送到晶片的多个开口。 电极组件具有第一电极部件和第二电极部件，该第二电极部件具有可操作地与晶片的周边部分和中心部分接合的通道。 通道将解决方案传输到面罩。

公开(公告)号：US09125333B2

公开(公告)日：2015-09-01

申请号：US13183870

申请日：2011-07-15

Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Belgacem Haba ,  Piyush Savalia ,  Craig Mitchell

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/40

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/056 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/013 ,  H05K1/09 ,  H05K3/4007 ,  H05K2201/032 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract translation: 用于电气应用的阻隔层。 在一些实施例中，阻挡层是层压阻挡层。 在一些实施例中，阻挡层包括梯度阻挡层。

公开(公告)号：US20130122747A1

公开(公告)日：2013-05-16

申请号：US13296785

申请日：2011-11-15

Applicant: Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

Inventor： Cyprian Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01R24/28

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another.

Abstract translation: 互连部件包括具有开口的元件，延伸穿过开口彼此电绝缘的多个导体以及彼此电绝缘的多个第二触点。 该元件由热膨胀系数小于10ppm /℃的材料构成。 至少一些导体沿开口的至少一个内表面延伸。 导体在第一表面限定多个可润湿的第一接触。 第一触点在厚度方向上与开口至少部分地对齐，并且彼此电绝缘。

公开(公告)号：US20130118784A1

公开(公告)日：2013-05-16

申请号：US13293698

申请日：2011-11-10

Applicant: Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

Inventor： Cyprian Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Philip Damberg

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.