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公开(公告)号：US20200293315A1
公开(公告)日：2020-09-17
申请号：US16427794
申请日：2019-05-31
Applicant: Graphcore Limited
Inventor： Jonathan Mangnall , Stephen Felix
Abstract: An execution unit is described which is particularly configured to generate an exponential of an operand floating point format. The operand is multiplied by a fixed multiplicant, logged to the base 2 (e) to generate a multiplication result. An integer part and a fractional part are extracted from the multiplication result. An exponent register stores the integer part to form the exponent of the exponential result. A lookup table has a plurality of entries each providing a value of 2f for a fractional part f used to access a lookup table. The fractional part is derived from a mantissa of the operand. That is, first and second bit sequences are extracted from the mantissa. One of the bit sequences is used to generate an estimated fractional component, and the other is used to access a value from the lookup table. The estimated fractional component and a looked up value are multiplied. It is possible to extract more than first and second bit sequences from the mantissa, in which case each of the additional bit sequences are used to access respective values from the lookup table.
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公开(公告)号：US20200183878A1
公开(公告)日：2020-06-11
申请号：US16790215
申请日：2020-02-13
Applicant: Graphcore Limited
Inventor： Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix
IPC: G06F15/173 , G06F15/80 , G06F9/52
Abstract: A computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising: a switch control instruction which when executed causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in the sequence of instructions and its execution by the execution unit.
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公开(公告)号：US10579582B2
公开(公告)日：2020-03-03
申请号：US15886340
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix
IPC: G06F15/00 , G06F15/173 , G06F9/52 , G06F15/80
Abstract: A computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising: a switch control instruction which when executed causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in the sequence of instructions and its execution by the execution unit.
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公开(公告)号：US20190121779A1
公开(公告)日：2019-04-25
申请号：US15886340
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Richard Luke Southwell Osborne , Alan Graham Alexander , Stephen Felix
IPC: G06F15/173 , G06F15/80 , G06F9/52
Abstract: A computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising: a switch control instruction which when executed causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in the sequence of instructions and its execution by the execution unit.
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公开(公告)号：US20190121680A1
公开(公告)日：2019-04-25
申请号：US15886065
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Daniel John Pelham Wilkinson , Stephen Felix , Matthew David Fyles , Richard Luke Southwell Osborne
Abstract: A processing system comprising: a subsystem for acting as a work accelerator to a host processor, the subsystem comprising an arrangement of tiles; and an interconnect for communicating between the tiles and connecting the subsystem to the host. The interconnect comprises synchronization logic to coordinate barrier synchronizations between a group of the tiles. The synchronization logic comprises a host sync proxy module, comprising a counter written with a number of credits by the host processor, and being configured to automatically decrement the number of credits each time one of the barrier synchronizations requiring host involvement is performed. When the number of credits in the counter is exhausted, the barrier is not released until a further write from the host to the host sync proxy module, but when the number is credits in the counter is not exhausted the barrier is released without a separate write from the host.
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Patent Agency Ranking
公开(公告)号：US20190121639A1
公开(公告)日：2019-04-25
申请号：US15886331
申请日：2018-02-01
Applicant: Graphcore Limited
Inventor： Stephen Felix , Simon Christian Knowles , Godfrey Da Costa
Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which when executed by the execution unit masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and the masked values in their respective original locations.
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公开(公告)号：US12032021B2
公开(公告)日：2024-07-09
申请号：US17934250
申请日：2022-09-22
Applicant: Graphcore Limited
Inventor： Stephen Felix , Phillip Horsfield
IPC: G01R31/3185 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/318555 , G01R31/31724 , G01R31/3177
Abstract: A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising: sending from testing logic of the first die, first testing control signals to first testing apparatus on the first die; in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die; sending from the testing logic of the first die, second testing control signals to the second die via through silicon vias formed in a substrate of the first die; and in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.
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公开(公告)号：US11940940B2
公开(公告)日：2024-03-26
申请号：US17658944
申请日：2022-04-12
Applicant: Graphcore Limited
Inventor： Daniel Wilkinson , Stephen Felix , Simon Knowles , Graham Cunningham , David Lacey
CPC classification number: G06F13/4022 , G06F9/30079 , G06F9/522 , G06F13/4027
Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.
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公开(公告)号：US11889615B2
公开(公告)日：2024-01-30
申请号：US17075350
申请日：2020-10-20
Applicant: Graphcore Limited
Inventor： Stephen Felix
CPC classification number: H05K1/0231 , H05K1/0215 , H05K1/032 , H05K1/184 , H05K3/0058 , H05K2201/0162
Abstract: There is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.
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公开(公告)号：US11886505B2
公开(公告)日：2024-01-30
申请号：US17658085
申请日：2022-04-05
Applicant: Graphcore Limited
Inventor： Jonathan Mangnall , Stephen Felix
IPC: G06F17/17 , G06F1/03 , G06F16/901
CPC classification number: G06F16/9017 , G06F1/03 , G06F17/17
Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.
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