公开(公告)号：US11532356B2

公开(公告)日：2022-12-20

申请号：US17223435

申请日：2021-04-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

公开(公告)号：US11462268B1

公开(公告)日：2022-10-04

申请号：US17245115

申请日：2021-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Can Li ,  Catherine Graves

IPC: G11C11/00 ,  G11C13/00 ,  H03K5/24

Abstract: Examples disclosed herein relate to digital hash code generation. A digital hash code generating device comprising a plurality of variable conductance elements. Each variable conductance element is coupled to a selected row line and to a selected column line of a crossbar array. Each variable conductance element comprises a conductance from a stochastic distribution of conductance. A plurality of comparator elements and each comparator element is connected to a set of at least two column lines. The plurality of comparator elements generates a hash code in response to a vector input applied to the plurality of row lines of the crossbar array.

公开(公告)号：US11294763B2

公开(公告)日：2022-04-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US11289162B2

公开(公告)日：2022-03-29

申请号：US16862997

申请日：2020-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Can Li

IPC: G11C15/04

Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.

公开(公告)号：US20210327508A1

公开(公告)日：2021-10-21

申请号：US17302439

申请日：2021-05-03

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C15/00

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

公开(公告)号：US10998047B1

公开(公告)日：2021-05-04

申请号：US16744136

申请日：2020-01-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C15/00

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

公开(公告)号：US20210050060A1

公开(公告)日：2021-02-18

申请号：US16539868

申请日：2019-08-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C8/12 ,  G11C11/413 ,  G11C11/408

Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.

公开(公告)号：US20250095736A1

公开(公告)日：2025-03-20

申请号：US18469457

申请日：2023-09-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Giacomo Pedretti ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04

Abstract: A technique for compressing an analog content addressable memory (CAM) array is provided. Random input data is applied to the analog CAM array, and an average measure of similarity is calculated for each output row of the analog CAM array. Rows of the analog CAM array that have measures of similarity that are close to each other can be eliminated, such as by removing similar rows or merging together similar rows. Thus, the analog CAM array size can be reduced without a loss in accuracy of a model stored on the analog CAM array.

公开(公告)号：US12205659B2

公开(公告)日：2025-01-21

申请号：US18483448

申请日：2023-10-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Giacomo Pedretti ,  John Paul Strachan ,  Catherine Graves

IPC: G11C27/00 ,  G11C15/04

Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

公开(公告)号：US12106805B2

公开(公告)日：2024-10-01

申请号：US17872882

申请日：2022-07-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Tobias Frederic Ziegler ,  Ron M. Roth ,  Giacomo Pedretti ,  Luca Buonanno ,  Pedro Henrique Rocha Bruel ,  Catherine Graves

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/12 ,  H03K19/017

CPC classification number: G11C15/04 ,  G11C16/102 ,  G11C16/12 ,  H03K19/01742

Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.