公开(公告)号：US10404625B2

公开(公告)日：2019-09-03

申请号：US14496667

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/939 ,  H04L1/16 ,  H04L12/947 ,  H04L12/861

Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.

公开(公告)号：US10073775B2

公开(公告)日：2018-09-11

申请号：US15089035

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Christopher B. Wilerkson ,  Ren Wang ,  Antoine Kaufmann ,  Anil Vasudevan ,  Robert G. Blankenship ,  Venkata Krishnan ,  Tsung-Yuan C. Tai

IPC: G06F12/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/0862 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.

公开(公告)号：US09979640B2

公开(公告)日：2018-05-22

申请号：US14580981

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Parthasarathy Sarangam ,  Eric Mann ,  Daniel Cohn

IPC: G06F11/00 ,  H04L12/741 ,  H04L12/801 ,  H04L12/873 ,  H04L12/863 ,  H04L12/721

CPC classification number: H04L45/74 ,  H04L45/38 ,  H04L47/115 ,  H04L47/52 ,  H04L47/54

Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

公开(公告)号：US09674098B2

公开(公告)日：2017-06-06

申请号：US14313740

申请日：2014-06-24

Applicant: INTEL CORPORATION

Inventor： Ilango Ganga ,  Alain Gravel ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson ,  Thomas D. Lovett

IPC: H04L1/00 ,  H04L12/851

CPC classification number: H04L47/2441 ,  Y02D30/30 ,  Y02D30/32

Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.

公开(公告)号：US09535838B2

公开(公告)日：2017-01-03

申请号：US13691106

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20160350250A1

公开(公告)日：2016-12-01

申请号：US15033484

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Anil Vasudevan ,  Eric Geisler ,  Marshall Marc Millier

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4282

Abstract: Techniques for handling unaligned data in a computing system are described herein. The techniques may include receiving data from an input/output (I/O) device, through an I/O interface. The data may be padded by adding values to the data at the I/O interface if the data is unaligned with respect to that computing system such that a consumer of the data associated with the I/O device ignores the added values.

Abstract translation: 本文描述了用于在计算系统中处理未对齐数据的技术。 这些技术可以包括通过I / O接口从输入/输出（I / O）设备接收数据。 如果数据相对于该计算系统未对齐，则可以通过将数值添加到I / O接口中的数据来填补数据，使得与I / O设备相关联的数据的消费者忽略添加的值。

公开(公告)号：US20150161050A1

公开(公告)日：2015-06-11

申请号：US14583601

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US09032103B2

公开(公告)日：2015-05-12

申请号：US13706575

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F5/00 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20150085873A1

公开(公告)日：2015-03-26

申请号：US14557020

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Tsao ,  Anil Vasudevan

IPC: H04L12/861 ,  H04L29/06

CPC classification number: H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US11816036B2

公开(公告)日：2023-11-14

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

CPC classification number: G06F12/0868 ,  G06F3/065 ,  G06F3/068 ,  G06F3/0619 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/311 ,  G06F2212/6046

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.