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公开(公告)号：US11703906B2
公开(公告)日：2023-07-18
申请号：US17520296
申请日：2021-11-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F9/30 , G06F9/455 , G06F1/324
CPC classification number: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30101 , G06F9/45558 , G06F2009/45591
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US11372464B2
公开(公告)日：2022-06-28
申请号：US15719481
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Fuat Keceli , Frederico Ardanaz , Jonathan M. Eastep , Ankush Varma , Krishnakanth V. Sistla
Abstract: An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.
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公开(公告)号：US20210334187A1
公开(公告)日：2021-10-28
申请号：US16860967
申请日：2020-04-28
Applicant: Intel Corporation
Inventor： Aman Sewani , Nazar Haider , Ankush Varma , Lan Vu
IPC: G06F11/30 , G06F1/3296 , G06F1/08
Abstract: A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.
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公开(公告)号：US10545793B2
公开(公告)日：2020-01-28
申请号：US15720296
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Vijay Dhanraj , Russell J. Fenger , Vivek Garg , Eugene Gorbatov , Stephen H. Gunther , Monica Gupta , Efraim Rotem , Krishnakanth V. Sistla , Guy M. Therien , Ankush Varma , Eliezer Weissmann
Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
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公开(公告)号：US20180067892A1
公开(公告)日：2018-03-08
申请号：US15811848
申请日：2017-11-14
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
CPC classification number: G06F15/00 , G06F1/206 , G06F1/26 , G06F1/3243 , G06F9/45541 , G06F9/45558 , G06F9/5077 , G06F9/5094 , G06F2009/4557 , Y02D10/152 , Y02D10/16
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20180004269A1
公开(公告)日：2018-01-04
申请号：US15197083
申请日：2016-06-29
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Alexander Gendler , Ankush Varma
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/28 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3243 , G06F1/325 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/44 , Y02D10/126 , Y02D10/152
Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.
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公开(公告)号：US20170102752A1
公开(公告)日：2017-04-13
申请号：US15296096
申请日：2016-10-18
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Allen W. Chu , Ian M. Steiner
CPC classification number: G06F1/3287 , G06F1/266 , G06F1/3293 , G06F1/3296 , G06F9/4893 , Y02D10/122 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
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公开(公告)号：US09557804B2
公开(公告)日：2017-01-31
申请号：US14867490
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
Abstract translation: 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，可以实现处理器和存储器模块之间的平台功率预算的动态共享。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。
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公开(公告)号：US09513688B2
公开(公告)日：2016-12-06
申请号：US13844815
申请日：2013-03-16
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Jeremy J. Shrall , Avinash N. Ananthakrishnan
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3206 , Y02D10/126
Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.
Abstract translation: 可扩展性算法使处理器初始化性能指标计数器，在第一时间信号的初始频率下操作第一持续时间，并且基于性能指标计数器确定第一处理核心的初始性能。 该算法然后可以使处理器在第一时钟信号的第二频率下工作持续第二持续时间，并且基于性能指标计数器确定第一处理核心的第二性能。 可以基于初始性能和第二性能来确定第一处理核心的性能可扩展性，并且可以基于所确定的可扩展性来改变诸如一个或多个时钟频率和/或供电电压的操作参数。
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公开(公告)号：US09495001B2
公开(公告)日：2016-11-15
申请号：US13972569
申请日：2013-08-21
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Allen W. Chu , Ian M. Steiner
CPC classification number: G06F1/3287 , G06F1/266 , G06F1/3293 , G06F1/3296 , G06F9/4893 , Y02D10/122 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，耦合到多个核心的功率传递逻辑，以及功率控制器，其包括使第一核心进入第一低功率状态的第一逻辑 在第一核心的至少一个线程的执行期间独立于OS的操作系统电源管理方案。 描述和要求保护其他实施例。
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