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41.发明授权公开(公告)号：US09939879B2
公开(公告)日：2018-04-10
申请号：US14875930
申请日：2015-10-06
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
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公开(公告)号：US09811355B2
公开(公告)日：2017-11-07
申请号：US14338692
申请日：2014-07-23
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Doron Rajwan , Nadav Shulman , Eliezer Weissmann
IPC: G06F1/32 , G06F9/445 , G06F12/0844 , G06F13/42
CPC classification number: G06F9/44505 , G06F1/324 , G06F12/0844 , G06F13/4234 , G06F2212/1052 , G06F2212/604 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
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公开(公告)号：US09792064B2
公开(公告)日：2017-10-17
申请号：US15219183
申请日：2016-07-25
Applicant: Intel Corporation
Inventor： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
CPC classification number: G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
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公开(公告)号：US20170168118A1
公开(公告)日：2017-06-15
申请号：US15357312
申请日：2016-11-21
Applicant: INTEL CORPORATION
Inventor： Efraim Rotem , NIR ROSENZWEIG , JEFFREY A. CARLSON , PHILIP R. LEHWALDER , NADAV SHULMAN , Doron Rajwan
IPC: G01R31/36 , G01R22/10 , G01R21/133
CPC classification number: G01R31/3648 , G01R21/133 , G01R22/10 , G01R31/3624
Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.
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公开(公告)号：US09671853B2
公开(公告)日：2017-06-06
申请号：US14484649
申请日：2014-09-12
Applicant: Intel Corporation
Inventor： Yoni Aizik , Eliezer Weissmann , Efraim Rotem , Yevgeni Sabin , Doron Rajwan , Ahmad Yasin
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20170097668A1
公开(公告)日：2017-04-06
申请号：US15381241
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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公开(公告)号：US20160313778A1
公开(公告)日：2016-10-27
申请号：US15138505
申请日：2016-04-26
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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公开(公告)号：US20160259389A1
公开(公告)日：2016-09-08
申请号：US15157553
申请日：2016-05-18
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
CPC classification number: G06F1/28 , G06F1/266 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。
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公开(公告)号：US20160077569A1
公开(公告)日：2016-03-17
申请号：US14484649
申请日：2014-09-12
Applicant: Intel Corporation
Inventor： Yoni Aizik , Eliezer Weissmann , Efraim Rotem , Yevgeni Sabin , Doron Rajwan , Ahmad Yasin
CPC classification number: G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括至少一个核心和能量性能增益（EPG）逻辑，以基于EPG的第一值来确定EPG频率。 EPG基于处理器消耗的能量和处理器的性能。 处理器还包括时钟发生器，用于基于EPG频率产生至少一个核心的操作频率。 描述和要求保护其他实施例。
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公开(公告)号：US20160070321A1
公开(公告)日：2016-03-10
申请号：US14482148
申请日：2014-09-10
Applicant: Intel Corporation
Inventor： Dorit Shapira , Efraim Rotem , Doron Rajwan , Nadav Shulman , Esfir Natanzon , Nir Rosenzweig
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核和耦合到核的功率控制单元（PCU）。 PCU具有应力检测器，用于接收处理器运行的电压和温度，并计算包括有效可靠性压力在内的寿命统计信息，在诸如个人计算机，服务器计算机等计算系统的多个引导周期之后维持寿命统计信息， 平板电脑，智能电话或任何其他计算平台，基于生存期统计信息来控制处理器的一个或多个操作参数，并且经由接口将至少一部分生命周期统计信息传达给用户和/或管理实体 的处理器。 描述和要求保护其他实施例。
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