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公开(公告)号：US10394300B2
公开(公告)日：2019-08-27
申请号：US15966397
申请日：2018-04-30
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
IPC: G06F1/28 , G06F1/3206 , G06F1/324 , G06F1/26
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
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公开(公告)号：US11175712B2
公开(公告)日：2021-11-16
申请号：US16527150
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
IPC: G06F1/28 , G06F1/324 , G06F1/3206 , G06F1/26 , G06F1/3296
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
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公开(公告)号：US20180314307A1
公开(公告)日：2018-11-01
申请号：US15966397
申请日：2018-04-30
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
CPC classification number: G06F1/28 , G06F1/266 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
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公开(公告)号：US10078590B2
公开(公告)日：2018-09-18
申请号：US15393883
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC: G06T9/00 , G06F12/0831 , G06F12/0817 , G06F12/0811 , G06T1/60 , G06F13/42 , G11C7/10 , G06F13/16 , G06F13/28
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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公开(公告)号：US09367114B2
公开(公告)日：2016-06-14
申请号：US13793037
申请日：2013-03-11
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
CPC classification number: G06F1/28 , G06F1/266 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US09035962B2
公开(公告)日：2015-05-19
申请号：US13844214
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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公开(公告)号：US20190354155A1
公开(公告)日：2019-11-21
申请号：US16527150
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
IPC: G06F1/28 , G06F1/26 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
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公开(公告)号：US09996135B2
公开(公告)日：2018-06-12
申请号：US15157553
申请日：2016-05-18
Applicant: Intel Corporation
Inventor： Ryan D. Wells , Itai Feit , Doron Rajwan , Nadav Shulman , Zeev Offen , Inder M. Sodhi
CPC classification number: G06F1/28 , G06F1/266 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
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公开(公告)号：US20170109287A1
公开(公告)日：2017-04-20
申请号：US15393907
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
IPC: G06F12/0831 , G06F13/42 , G11C7/10 , G06F12/0811
CPC classification number: G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
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10.发明授权Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods 有权用于集成电路的电路块之间的通信的接口以及相关联的设备，系统和方法公开(公告)号：US09594413B2
公开(公告)日：2017-03-14
申请号：US14140219
申请日：2013-12-24
Applicant: INTEL CORPORATION
Inventor： Ivan Herrera Mejia , Zeev Offen
CPC classification number: G06F1/26 , G06F1/24 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/24 , G06F9/4418 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.
Abstract translation: 包括相关联的系统，方法和装置的实施例，其提供了芯片上系统（SoC）的北复合体和南复合体之间的接口。 在实施例中，北复合体可以包括输入信号要求中的微控制器。 上电控制块可以与微控制器耦合，并且上电控制块可以被配置为从南复合体的组件接收控制信号，并且至少部分地基于输入信号来改变控制信号 要求微控制器。
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