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    DATA TAINTING TO MITIGATE SPECULATION VULNERABILITIES
    41.
    发明申请
    DATA TAINTING TO MITIGATE SPECULATION VULNERABILITIES 有权

    公开(公告)号：US20220207149A1

    公开(公告)日：2022-06-30

    申请号：US17134347

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Jason W. Brandt ,  Joseph Nuzman ,  Asit Mallick ,  Carlos Rozas

    IPC: G06F21/57 ,  G06F21/75 ,  G06F21/53

    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability detection hardware and execution hardware. The speculation vulnerability detection hardware is to detect vulnerability to a speculative execution attack and, in connection with a detection of vulnerability to a speculative execution attack, to provide an indication that data from a first operation is tainted. The execution hardware is to perform a second operation using the data if the second operation is to be performed non-speculatively and to prevent performance of the second operation if the second operation is to be performed speculatively and the data is tainted.

    MEMORY BANDWIDTH MONITORING EXTENSIBLE COUNTER
    43.
    发明申请
    MEMORY BANDWIDTH MONITORING EXTENSIBLE COUNTER 有权

    公开(公告)号：US20220206797A1

    公开(公告)日：2022-06-30

    申请号：US17134256

    申请日：2020-12-25

    Applicant: Intel Corporation

    Inventor： Andrew J. Herdrich ,  Jason W. Brandt

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Embodiments of apparatuses and methods for memory bandwidth monitoring extensible counters are described. In embodiments, an apparatus includes memory bandwidth monitoring hardware to monitor an event, a shared cache to be shared by multiple cores. At least one of the cores is to execute multiple threads and includes at least three registers. The first register is programmable by software to store a thread identifier of one of threads and an event identifier of the event during execution of the thread. At least one value of the event identifier corresponds to a shared cache miss. The second register is to provide to the software a second value corresponding to a number of bits available to represent the count. The third register is to provide to the software a count of occurrences of the event and an indicator to indicate whether the count reached a maximum count representable by the number of bits.

    Processor extensions to protect stacks during ring transitions
    45.
    发明授权
    Processor extensions to protect stacks during ring transitions 有权

    公开(公告)号：US11176243B2

    公开(公告)日：2021-11-16

    申请号：US16585373

    申请日：2019-09-27

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

    IPC: G06F21/52 ,  G06F3/06 ,  G06F12/14 ,  G06F9/30 ,  G06F9/46

    Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

    Hardware apparatuses and methods to switch shadow stack pointers
    47.
    发明授权
    Hardware apparatuses and methods to switch shadow stack pointers 有权

    公开(公告)号：US11029952B2

    公开(公告)日：2021-06-08

    申请号：US16534970

    申请日：2019-08-07

    Applicant: Intel Corporation

    Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

    IPC: G06F9/30 ,  G06F9/46 ,  G06F21/52

    Abstract: Methods and apparatuses relating to switching of a shadow stack pointer are described. In one embodiment, a hardware processor includes a hardware decode unit to decode an instruction, and a hardware execution unit to execute the instruction to: pop a token for a thread from a shadow stack, wherein the token includes a shadow stack pointer for the thread with at least one least significant bit (LSB) of the shadow stack pointer overwritten with a bit value of an operating mode of the hardware processor for the thread, remove the bit value in the at least one LSB from the token to generate the shadow stack pointer, and set a current shadow stack pointer to the shadow stack pointer from the token when the operating mode from the token matches a current operating mode of the hardware processor.

    Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
    48.
    发明授权
    Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width 有权

    公开(公告)号：US10901940B2

    公开(公告)日：2021-01-26

    申请号：US15089525

    申请日：2016-04-02

    Applicant: INTEL CORPORATION

    Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

    IPC: G06F9/30 ,  G06F15/80

    Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

    VIRTUALIZING PRECISE EVENT BASED SAMPLING
    49.
    发明申请
    VIRTUALIZING PRECISE EVENT BASED SAMPLING 审中-公开

    公开(公告)号：US20200242003A1

    公开(公告)日：2020-07-30

    申请号：US16699871

    申请日：2019-12-02

    Applicant: Intel Corporation

    Inventor： Matthew C. Merten ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Grant G. Zhou ,  Andreas Kleen ,  Kimberly C. Weier ,  Angela D. Schmid ,  Stanislav Bratanov ,  Seth Abraham ,  Jason W. Brandt ,  Ahmad Yasin

    IPC: G06F11/36 ,  G06F9/455

    Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.

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