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公开(公告)号：US09465680B1
公开(公告)日：2016-10-11
申请号：US14721819
申请日：2015-05-26
Applicant: INTEL CORPORATION
Inventor： Michael W. Chynoweth , Jonathan D. Combs , Angela D. Schmid , Kimberly C. Weier , Ahmad Yasin , Jason W. Brandt , Charlie J. Hewett , Seth Abraham , Matthew C. Merten
CPC classification number: G06F9/542 , G06F11/00 , G06F11/3024 , G06F11/3409
Abstract: A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.
Abstract translation: 描述了使用固定功能性能计数器实现性能监视的处理器和方法。 例如，设备的一个实施例包括：固定功能性能计数器，用于在处理设备中发生事件时递减或递增; 精确的基于事件的采样（PEBS）使能控制可通信地耦合到固定功能性能计数器; PEBS处理器，用于生成和存储PEBS记录，其包括在生成PEBS记录时定义处理设备的状态的架构元数据; 以及可通信地耦合到PEBS使能控制和PEBS处理器的非精确事件采样（NPEBS）模块，NPEBS模块使固定功能性能计数器达到指定值时使PEBS处理程序生成事件的PEBS记录 。
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Patent Agency Ranking
公开(公告)号：US09965375B2
公开(公告)日：2018-05-08
申请号：US15194881
申请日：2016-06-28
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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公开(公告)号：US11055203B2
公开(公告)日：2021-07-06
申请号：US16699871
申请日：2019-12-02
Applicant: Intel Corporation
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US20200242003A1
公开(公告)日：2020-07-30
申请号：US16699871
申请日：2019-12-02
Applicant: Intel Corporation
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US20180253370A1
公开(公告)日：2018-09-06
申请号：US15972390
申请日：2018-05-07
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A processor is to execute and retire instructions for a virtual machine. A reload register is coupled to the core is to store a reload value. A performance monitoring counter (PMC) register is coupled to the reload register and an event-based sampler operatively is coupled to the reload register and the PMC register. The event-based sampler includes circuitry to load the reload value into the PMC register and increment the PMC register after detecting each occurrence of an event of a certain type as a result of execution of the instructions. Upon detecting an occurrence of the event after the PMC register reaches a predetermined trigger value, the event-based sampler is to execute microcode to generate field data for elements within a sampling record, wherein the field data relates to a current processor state of execution, and reload the reload value from the reload register into the PMC register.
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公开(公告)号：US20170371769A1
公开(公告)日：2017-12-28
申请号：US15194881
申请日：2016-06-28
Applicant: INTEL CORPORATION
Inventor： Matthew C. Merten , Beeman C. Strong , Michael W. Chynoweth , Grant G. Zhou , Andreas Kleen , Kimberly C. Weier , Angela D. Schmid , Stanislav Bratanov , Seth Abraham , Jason W. Brandt , Ahmad Yasin
CPC classification number: G06F11/3636 , G06F9/45558 , G06F2009/45591 , H04L41/0613 , H04L43/04
Abstract: A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as trace data packets. An event-based sampler generates field data for a sampling record in response to occurrence of an event of a certain type as a result of execution of the instruction. The processor tracer, upon receipt of the field data: formats the field data into elements of the sampling record as a group of record packets; inserts the group of record packets between the trace data packets as a combined packet stream; and stores the combined packet stream in the memory buffer as a series of output pages. The core, when in guest profiling mode, executes a virtual machine monitor to map output pages of the memory buffer to host physical pages of main memory using multilevel page tables.
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