公开(公告)号：US11169850B2

公开(公告)日：2021-11-09

申请号：US16726341

申请日：2019-12-24

Applicant: Intel Corporation

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06F9/48 ,  G06T1/20 ,  G06T15/00 ,  G06T1/60

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US11081091B2

公开(公告)日：2021-08-03

申请号：US16658793

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08 ,  G06F3/14 ,  G09G5/36

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US10852806B2

公开(公告)日：2020-12-01

申请号：US16661803

申请日：2019-10-23

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Kiran C. Veernapu ,  Eric J. Asperheim ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F15/00 ,  G06F1/3234 ,  G06F9/46 ,  G06F1/329

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

公开(公告)号：US10761898B2

公开(公告)日：2020-09-01

申请号：US15672086

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Varghese George ,  Inder M. Sodhi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

公开(公告)号：US20200160819A1

公开(公告)日：2020-05-21

申请号：US16658793

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08 ,  G06F3/14 ,  G09G5/36

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US10521271B2

公开(公告)日：2019-12-31

申请号：US15477026

申请日：2017-04-01

Applicant: INTEL CORPORATION

Inventor： Abhishek R Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06F1/329 ,  G06T1/20 ,  G06T1/60 ,  G06F9/48 ,  G06T15/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US10430310B2

公开(公告)日：2019-10-01

申请号：US15477031

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Balaji Vembu ,  Josh B. Mastronarde ,  Altug Koker ,  Eric C. Samson ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F1/00 ,  G06F11/30 ,  G06F1/3206 ,  G06F1/3296 ,  G05F1/10 ,  G05F1/571 ,  G06F11/32 ,  G06F11/34 ,  G06F1/324

Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190266981A1

公开(公告)日：2019-08-29

申请号：US16400919

申请日：2019-05-01

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F3/14 ,  G09G5/36 ,  G09G5/02 ,  H03K19/00 ,  G09G5/34 ,  G06F13/40 ,  H03K19/08 ,  G09G5/37

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180341306A1

公开(公告)日：2018-11-29

申请号：US16056964

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Satish K. Damaraju ,  Yun-Han Chen ,  Ryan D. Wells ,  Inder M. Sodhi ,  Vishram Sarurkar ,  Ken Drottar ,  Ashish V. Choubal ,  Rabiul Islam

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D10/22

Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

公开(公告)号：US10139882B2

公开(公告)日：2018-11-27

申请号：US15174779

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Sanjeev S. Jahagirdar ,  Inder M. Sodhi ,  Jeremy J. Shrall ,  Stephen H. Gunther ,  Daniel J. Ragland ,  Nicholas J. Adams

IPC: G06F1/28 ,  G06F1/26 ,  G06F1/24 ,  G06F1/32 ,  G06F9/448

Abstract: According to one embodiment of the invention, a processor includes a power control unit, an interface to software during runtime that permits the software to set a plurality of power management constraint parameters for the power control unit during runtime of the processor without a reboot of the processor, and a storage element to store a respective lock bit for each of the plurality of power management constraint parameters to disable the interface from changing a respective constraint parameter when set.