公开(公告)号：US20240063120A1

公开(公告)日：2024-02-22

申请号：US17820961

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Debendra Mallik ,  Christopher M. Pelto ,  Kimin Jun ,  Johanna M. Swan ,  Lei Jiang ,  Feras Eid ,  Krishna Vasanth Valavala ,  Henning Braunisch ,  Patrick Morrow ,  William J. Lambert

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L23/5286 ,  H01L24/08 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5226 ,  H01L24/80 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16225

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

公开(公告)号：US11804456B2

公开(公告)日：2023-10-31

申请号：US16107791

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Omkar Karhade ,  Martin Rodriguez ,  Gregorio R. Murtagian

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/495 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/49582 ,  H01L23/5226 ,  H01L28/10

Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.

公开(公告)号：US11699630B2

公开(公告)日：2023-07-11

申请号：US17721127

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： William J. Lambert

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4882 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1427 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed.

公开(公告)号：US11616283B2

公开(公告)日：2023-03-28

申请号：US16122609

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  William J. Lambert ,  Xiaoqian Li ,  Sidharth Dalmia

IPC: H01Q1/22 ,  H03F3/195 ,  H03F3/24 ,  H01Q1/02 ,  H05K1/03

Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.

公开(公告)号：US11355849B2

公开(公告)日：2022-06-07

申请号：US16635148

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Shawna M. Liff ,  William J. Lambert ,  Zhichao Zhang ,  Robert L. Sankman ,  Sri Chaitra J. Chavali

IPC: H01Q9/04 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US20190279973A1

公开(公告)日：2019-09-12

申请号：US16426939

申请日：2019-05-30

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadla ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01L25/16 ,  H01L23/64 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01F17/00 ,  H01L23/00

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material: a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US10340260B2

公开(公告)日：2019-07-02

申请号：US15911958

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadala ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01F17/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/64

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US10157860B2

公开(公告)日：2018-12-18

申请号：US15392145

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Kedar Dhane ,  Yongki Min ,  William J. Lambert

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.

公开(公告)号：US20180197845A1

公开(公告)日：2018-07-12

申请号：US15911958

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Yongki Min ,  Reynaldo A. Olmedo ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Leigh E. Wojewoda ,  Venkat Anil K. Magadala ,  Clive R. Hendricks

IPC: H01L25/18 ,  H01L25/065 ,  H01F17/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01F17/00 ,  H01F17/0006 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16265 ,  H01L2924/1427 ,  H01L2924/143 ,  H01L2924/19011 ,  H01L2924/19042

Abstract: An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements arranged in the module substrate, wherein an inductive circuit element includes conductive traces arranged as a coil including a first coil end, a second coil end and a coil core, wherein the coil core includes the magnetic dielectric material; and a plurality of conductive contact pads electrically coupled to the first and second coil ends. The contact pads electrically coupled to the first coil ends are arranged on a first surface of the inductor module, and the contact pads electrically coupled to the second coil ends are arranged on a second surface of the inductor module.

公开(公告)号：US09992871B2

公开(公告)日：2018-06-05

申请号：US14937047

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mathew J Manusharow

IPC: H05K1/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/4644 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/0776 ,  H05K2201/09627 ,  H05K2201/10015 ,  H05K2203/14

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.