公开(公告)号：US20190393889A1

公开(公告)日：2019-12-26

申请号：US16541466

申请日：2019-08-15

Applicant: International Business Machines Corporation

Inventor： Anthony T. Sofia ,  Matthias Klein ,  Peter G. Sutton

IPC: H03M7/30

Abstract: A computer system includes a hardware controller and an internal millicode storage area. The controller includes an accelerator that decompresses a data stream requested by an application. The internal millicode storage area can store a compression dictionary library including a plurality of different pre-defined compression dictionaries. A host system includes a dictionary manager that determines a compression dictionary from the plurality of different pre-defined compression dictionaries included in the dictionary library to decompress the data stream. The accelerator can access the internal millicode storage area to obtain the determined compression dictionary, and to decompress the data stream according to the determined compression dictionary.

公开(公告)号：US20190312590A1

公开(公告)日：2019-10-10

申请号：US15948659

申请日：2018-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony T. Sofia ,  Jonathan D. Bradbury ,  Matthias Klein ,  Peter Sutton

IPC: H03M7/30 ,  H03M7/40 ,  G06F8/65 ,  G06F8/61

Abstract: A computer system includes a hardware controller and a host system. The hardware controller includes an accelerator to encode a data stream requested by an application based on a version of the accelerator. The host system executes a compression library linked to the application. The compression library operates according to one or more behavior characteristics to execute a compression algorithm that compresses the encoded data provided by the hardware controller. The behavior characteristics of the compression library is actively changed based on the version of the accelerator.

公开(公告)号：US20190220323A1

公开(公告)日：2019-07-18

申请号：US15873963

申请日：2018-01-18

Applicant: International Business Machines Corporation

Inventor： Brenton F. Belmar ,  Christian Jacobi ,  Matthias Klein ,  Peter G. Sutton

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/5077

Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator. An output work package is provided from the hardware accelerator in groups of one or more pages to the application.

公开(公告)号：US10353833B2

公开(公告)日：2019-07-16

申请号：US15646340

申请日：2017-07-11

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish G. Kurup

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US10275354B2

公开(公告)日：2019-04-30

申请号：US16103253

申请日：2018-08-14

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F12/0831 ,  G06F12/1009 ,  G06F12/1027

Abstract: A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

公开(公告)号：US10229084B2

公开(公告)日：2019-03-12

申请号：US15190250

申请日：2016-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott A. Brewer ,  David F. Craddock ,  Matthew J. Kalos ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40 ,  G06F13/28

Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

公开(公告)号：US10223308B2

公开(公告)日：2019-03-05

申请号：US15808071

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F13/42 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1027

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US10210131B2

公开(公告)日：2019-02-19

申请号：US15209111

申请日：2016-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David F. Craddock ,  Matthias Klein ,  Eric N. Lais

IPC: G06F12/00 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40 ,  G06F12/0862

Abstract: Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.

公开(公告)号：US20190018804A1

公开(公告)日：2019-01-17

申请号：US15806407

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish Kurup

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/1626 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4013 ,  G06F13/42

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US20190018803A1

公开(公告)日：2019-01-17

申请号：US15646340

申请日：2017-07-11

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish Kurup

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F13/1626 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4013 ,  G06F13/42

Abstract: A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.