公开(公告)号：US20180005838A1

公开(公告)日：2018-01-04

申请号：US15707176

申请日：2017-09-18

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Michael Roesner ,  Georg Ehrentraut

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/67 ,  H01L21/78

CPC classification number: H01L21/3065 ,  H01J37/32642 ,  H01J37/32651 ,  H01L21/67092 ,  H01L21/78

Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

公开(公告)号：US20170358494A1

公开(公告)日：2017-12-14

申请号：US15182387

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Gudrun Stranzl

IPC: H01L21/78 ,  H01L21/3065 ,  H01J37/32 ,  H01L29/16 ,  H01L23/495 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/1608 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

公开(公告)号：US20170148981A1

公开(公告)日：2017-05-25

申请号：US15427905

申请日：2017-02-08

Applicant: Infineon Technologies AG

Inventor： Carsten von Koblinski ,  Volker Strutz ,  Manfred Engelhardt

IPC: H01L43/14 ,  H01L27/12 ,  H01L23/00 ,  H01L43/04 ,  H01L43/06 ,  H01L23/31 ,  H01L21/84 ,  H01L27/22

CPC classification number: H01L43/14 ,  H01L21/78 ,  H01L21/84 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/06 ,  H01L27/12 ,  H01L27/22 ,  H01L43/04 ,  H01L43/065 ,  H01L43/12 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a method of forming a current sensor device includes forming a device region comprising a magnetic sensor within and/or over a semiconductor substrate. The device region is formed adjacent a front side of the semiconductor substrate. The back side of the semiconductor substrate is attached over an insulating substrate, where the back side is opposite the front side. Sidewalls of the semiconductor substrate are exposed by dicing the semiconductor substrate from the front side without completely dicing the insulating substrate. An isolation liner is formed over all of the exposed sidewalls of the semiconductor substrate. The isolation liner and the insulating substrate include a different material. The method further includes separating the insulating substrate to form diced chips, removing at least a portion of the isolation liner from over a top surface of the device region, and forming contacts over the top surface of the device region.

公开(公告)号：US09613848B2

公开(公告)日：2017-04-04

申请号：US14621082

申请日：2015-02-12

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/76227 ,  H01L21/02129 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/76804

Abstract: A method for forming a dielectric structure includes forming an auxiliary layer over a substrate, and forming a hole within the auxiliary layer. A fill material is deposited into the hole. The auxiliary layer is removed to form the dielectric structure having a negative taper. The dielectric structure has a top critical dimension greater than a bottom critical dimension.

公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20170076962A1

公开(公告)日：2017-03-16

申请号：US15358962

申请日：2016-11-22

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt

IPC: H01L21/67 ,  H01L21/683 ,  H01J37/32

CPC classification number: H01L21/67069 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32724 ,  H01J2237/332 ,  H01J2237/3341 ,  H01L21/6831 ,  Y10T279/21

Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.

Abstract translation: 公开了一种卡盘，包括卡盘的系统和制造半导体器件的方法。 在一个实施例中，卡盘包括被配置为电容耦合到第一RF功率发生器的第一导电区域，被配置为电容耦合到第二RF发电机的第二导电区域和将第一导电区域与 第二导电区域。

公开(公告)号：US20160343574A1

公开(公告)日：2016-11-24

申请号：US14717780

申请日：2015-05-20

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Michael Roesner ,  Georg Ehrentraut

IPC: H01L21/3065 ,  H01L29/06 ,  H01L21/78

CPC classification number: H01L21/3065 ,  H01J37/32642 ,  H01J37/32651 ,  H01L21/67092 ,  H01L21/78

Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

Abstract translation: 用于等离子体切割晶片的分段边缘保护屏蔽。 分段边缘保护屏蔽包括外部结构和多个等离子体屏蔽边缘段。 外部结构限定了内部环形边缘，其构造成对应于晶片的周边边缘。 多个等离子体屏蔽边缘段中的每一个由内边缘和侧边缘限定。 内边缘位于外部结构的环形边缘的内部并与其同心。 侧边缘在内边缘和环形边缘之间延伸。

公开(公告)号：US09490103B2

公开(公告)日：2016-11-08

申请号：US14977625

申请日：2015-12-21

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Gudrun Stranzl ,  Markus Zundel ,  Hubert Maier

IPC: H01L21/683 ,  H01L21/78 ,  H01J37/32 ,  B28D5/00

CPC classification number: H01J37/32009 ,  B28D5/00 ,  H01J2237/334 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

公开(公告)号：US09455192B2

公开(公告)日：2016-09-27

申请号：US14226666

申请日：2014-03-26

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Johann Schmid ,  Gudrun Stranzl ,  Joachim Hirschler

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/768 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/7806 ,  H01L21/02057 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.

Abstract translation: 根据本发明的实施例，一种形成半导体器件的方法包括：使用粘合剂组件将衬底附着到载体上，并通过衬底形成通孔以暴露粘合剂组分。 蚀刻粘合剂组分的至少一部分，并且在通孔的侧壁上形成金属层。

公开(公告)号：US09406564B2

公开(公告)日：2016-08-02

申请号：US14086886

申请日：2013-11-21

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Johannes Baumgartl ,  Manfred Kotek ,  Hans-Joachim Schulze

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/78 ,  H01L21/683 ,  H01L21/265

CPC classification number: H01L21/8234 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/32 ,  H01L21/6835 ,  H01L21/78 ,  H01L29/6659 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Abstract translation: 在一个实施例中，半导体管芯包括包括器件区域的选择性外延层和设置在外延层的侧壁周围的掩模结构。 掩模结构是半导体管芯的暴露表面的一部分。