公开(公告)号：US20160343392A1

公开(公告)日：2016-11-24

申请号：US14717213

申请日：2015-05-20

Applicant: Infineon Technologies AG

Inventor： Wolfgang Raberg ,  Andreas Strasser ,  Hermann Wendt ,  Klemens Pruegl

IPC: G11B5/39

CPC classification number: G11B5/3903 ,  G01R33/09 ,  G11B5/3909 ,  G11B2005/3996

Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

Abstract translation: 可以包括磁阻堆叠和设置在磁阻堆叠上的蚀刻停止层（ESL）的磁阻器件。 制造磁阻器件的方法可以包括：在衬底上沉积磁阻堆叠，ESL和掩模层; 执行第一蚀刻工艺以蚀刻掩模层的一部分以暴露ESL的一部分; 以及执行第二蚀刻工艺以蚀刻ESL的暴露部分和磁阻堆叠的一部分。 该方法还可以包括在第一蚀刻工艺之前在硬掩模上沉积光致抗蚀剂层，并且在第一蚀刻工艺之后从硬掩模中除去光致抗蚀剂层。 第一和第二蚀刻工艺可以不同。 例如，第一蚀刻工艺可以是反应性蚀刻工艺，第二蚀刻工艺可以是非反应性蚀刻工艺。

公开(公告)号：US10157765B2

公开(公告)日：2018-12-18

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/283 ,  H01L21/78 ,  H01L21/033 ,  H01L21/285 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

公开(公告)号：US20150084196A1

公开(公告)日：2015-03-26

申请号：US14507506

申请日：2014-10-06

Applicant: Infineon Technologies AG

Inventor： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Abstract translation: 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US09293371B2

公开(公告)日：2016-03-22

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

公开(公告)号：US20150294911A1

公开(公告)日：2015-10-15

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20150372073A1

公开(公告)日：2015-12-24

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Abstract translation: 公开了一种电子设备和电子设备的制造方法。 在一个实施例中，该方法包括在隔离层中形成开口，各向同性地蚀刻开口，从而形成具有弯曲侧壁的延伸开口，并在开口中形成导电材料。

公开(公告)号：US20140357055A1

公开(公告)日：2014-12-04

申请号：US13903013

申请日：2013-05-28

Applicant: Infineon Technologies AG

Inventor： Anja Gissibl ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US09959890B2

公开(公告)日：2018-05-01

申请号：US15400521

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Wolfgang Raberg ,  Andreas Strasser ,  Hermann Wendt ,  Klemens Pruegl

IPC: G11B5/39 ,  G01R33/09

CPC classification number: G11B5/3903 ,  G01R33/09 ,  G11B5/3909 ,  G11B2005/3996

Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

公开(公告)号：US09780161B2

公开(公告)日：2017-10-03

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01F17/02 ,  H01F38/14 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528 ,  H01L27/08 ,  H01L21/768 ,  H01L21/50 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.