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公开(公告)号：US20170041001A1
公开(公告)日：2017-02-09
申请号：US15331280
申请日：2016-10-21
Applicant: INTEL CORPORATION
Inventor： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
CPC classification number: H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
Abstract translation: 描述了一种装置，其包括：夹紧器，其耦合在第一电源和第二电源之间，所述夹具包括多个晶体管，用于与所述第二电源一起操作的电路; 以及控制单元，用于在所述设备进入低功率模式时接通和断开所述多个晶体管以调节所述第二电源。 控制单元包括用于将第二电源与第一参考值进行比较的第一比较器，将第二电源与第二参考电压进行比较的第二比较器和计数器。 当第二电源高于第一个参考电压时，计数器递增计数，当第二个电源低于第二个参考电压时，计数器递减计数。
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公开(公告)号：US09299412B2
公开(公告)日：2016-03-29
申请号：US14191191
申请日：2014-02-26
Applicant: Intel Corporation
Inventor： Helia Naeimi , Shih-Lien L. Lu , Charles Augustine
CPC classification number: G11C11/1675 , G11C7/1009 , G11C11/1657
Abstract: In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
Abstract translation: 在一个实施例中，控制器包括用于识别要被设置为并行状态的一行自旋转移转矩（STT）存储器中的第一个多个单元的逻辑，以及STT存储器的行中的第二多个单元 被设置为反并行状态，对行中的第二多个单元进行掩模写入操作，将第一多个单元设置为并行状态，对该行中的第一多个单元进行掩码写入操作，并将 第二多个单元格到反并行状态。
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公开(公告)号：US20150243335A1
公开(公告)日：2015-08-27
申请号：US14191191
申请日：2014-02-26
Applicant: Intel Corporation
Inventor： Helia Naeimi , Shih-Lien L. Lu , Charles Augustine
IPC: G11C11/16
CPC classification number: G11C11/1675 , G11C7/1009 , G11C11/1657
Abstract: In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.
Abstract translation: 在一个实施例中，控制器包括用于识别要被设置为并行状态的一行自旋转移转矩（STT）存储器中的第一个多个单元的逻辑，以及STT存储器的行中的第二多个单元 被设置为反并行状态，对行中的第二多个单元进行掩模写入操作，将第一多个单元设置为并行状态，对该行中的第一多个单元进行掩码写入操作，并将 第二多个单元格到反并行状态。
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公开(公告)号：US12007826B2
公开(公告)日：2024-06-11
申请号：US17128076
申请日：2020-12-19
Applicant: Intel Corporation
Inventor： Charles Augustine , Pascal Meinerzhagen , Suyoung Bang , Abdullah Afzal , Karthik Subramanian , Muhammad Khellah , Arvind Raman
IPC: G06F1/32 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/324 , G06F1/3296 , H03K19/0175
CPC classification number: G06F1/324 , G06F1/08 , G06F1/12 , G06F1/3296 , H03K19/017509
Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).
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公开(公告)号：US20240053987A1
公开(公告)日：2024-02-15
申请号：US17887154
申请日：2022-08-12
Applicant: Intel Corporation
Inventor： Charles Augustine , Seenivasan Subramaniam , Patrick Morrow , Muhammad M. Khellah
IPC: G06F9/30
CPC classification number: G06F9/30141 , G06F9/3012
Abstract: An apparatus, system, and method for register file circuits are provided. A register file circuit can include a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, a second PMOS transistor including a source coupled to an output of the first inverter, and a second WBL (WBLB) coupled to a drain of the second PMOS transistor. 1R1W register file and 2R1W register file designs are provided.
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Patent Agency Ranking
公开(公告)号：US11320888B2
公开(公告)日：2022-05-03
申请号：US16124071
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Charles Augustine , Muhammad Khellah , Arvind Raman , Ashish Choubal , Karthik Subramanian , Abdullah Afzal , Feroze Merchant
IPC: G06F1/00 , G06F1/3234 , H02M3/157 , G06F1/324 , H02M1/00
Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.
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公开(公告)号：US20210193196A1
公开(公告)日：2021-06-24
申请号：US16725747
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Charles Augustine , Somnath Paul , Turbo Majumder , Iqbal Rajwani , Andrew Lines , Altug Koker , Lakshminarayanan Striramassarma , Muhammad Khellah
Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.
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公开(公告)号：US20200081512A1
公开(公告)日：2020-03-12
申请号：US16124071
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Charles Augustine , Muhammad Khellah , Arvind Raman , Ashish Choubal , Karthik Subramanian , Abdullah Afzal , Feroze Merchant
Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.
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公开(公告)号：US20200005468A1
公开(公告)日：2020-01-02
申请号：US16565304
申请日：2019-09-09
Applicant: Intel Corporation
Inventor： Somnath Paul , Turbo Majumder , Mohamed Elmalaki , Muhammad Khellah , Charles Augustine
Abstract: Methods, systems, and articles herein are directed to event-driven object segmentation to track events rather than tracking all pixel locations in an image.
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公开(公告)号：US10403266B2
公开(公告)日：2019-09-03
申请号：US15786803
申请日：2017-10-18
Applicant: Intel Corporation
Inventor： Muhammad Khellah , Oren Arad , Binuraj Ravindran , Somnath Paul , Charles Augustine , Bruno Umbria Pedroni
Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.
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