公开(公告)号：US20190268803A1

公开(公告)日：2019-08-29

申请号：US16409245

申请日：2019-05-10

Applicant: Intel Corporation

Inventor： Hong He ,  Gang Xiong ,  Debdeep Chatterjee ,  Yushu Zhang

IPC: H04W28/04 ,  H04W72/12 ,  H04L5/00 ,  H04L5/14 ,  H04L1/18

Abstract: Embodiments of a User Equipment (UE), Next Generation Node-B (gNB) and methods of communication are generally described herein. The UE may receive radio resource control (RRC) signaling that configures reception of a plurality of physical downlink shared channels (PDSCHs) in a frame. The frame may comprise multiple slots, including one or more downlink slots and one or more uplink slots. The UE may determine a subset of the PDSCHs, such that for each of the PDSCHs of the subset, corresponding consecutive slots do not overlap the uplink slots. The UE may set a number of bits of a hybrid automatic repeat request acknowledgement (HARQ-ACK) codebook equal to a number of PDSCHs in the determined subset.

公开(公告)号：US10231264B2

公开(公告)日：2019-03-12

申请号：US15643237

申请日：2017-07-06

Applicant: INTEL CORPORATION

Inventor： Debdeep Chatterjee ,  Jong-Kae Fwu ,  Alexey Khoryaev ,  Hong He ,  Mikhail A. Shilov ,  Andrey Chervyakov ,  Sergey Panteleev

IPC: H04W74/08 ,  H04W28/08 ,  H04W4/06 ,  H04L5/14 ,  H04L5/00 ,  H04W28/02 ,  H04W72/04 ,  H04W24/10 ,  H04W36/08 ,  H04W24/02 ,  H04W72/08 ,  H04W76/19 ,  H04W4/70 ,  H04W76/10 ,  H04L12/18 ,  H04W36/00

Abstract: Technology for a first eNodeB is disclosed. The first eNodeB can decode an uplink-downlink (UL-DL) time-division duplexing (TDD) subframe reconfiguration received from a second eNodeB. The UL-DL TDD subframe reconfiguration can be for the first eNodeB. The first eNodeB can encode the UL-DL TDD subframe reconfiguration received from the second eNodeB for transmission to a plurality of user equipment (UEs).

公开(公告)号：US10097323B2

公开(公告)日：2018-10-09

申请号：US15408223

申请日：2017-01-17

Applicant: Intel Corporation

Inventor： Debdeep Chatterjee ,  Kamran Etemad ,  Rongzhen Yang ,  Jong-Kae Fwu ,  Apostolos Papathanassiou

IPC: H04L5/00 ,  H04W72/08 ,  H04B7/06 ,  H04W48/16 ,  H04W52/02 ,  H04W76/04 ,  H04W76/27

Abstract: Disclosed embodiments may include an apparatus having one or more processors coupled to one or more computer-readable storage media. The one or more processors may be configured to transmit and/or receive channel state information reference signal (CSI-RS) resource configuration information, demodulation reference signals (DM-RS), uplink sounding reference signals (SRS), and power control parameters to support uplink coordinated multi-point (CoMP) operations. Other embodiments may be disclosed.

公开(公告)号：US20180184423A1

公开(公告)日：2018-06-28

申请号：US15839599

申请日：2017-12-12

Applicant: Intel Corporation

Inventor： Sergey Panteleev ,  Alexey Khoryaev ,  Debdeep Chatterjee ,  Sergey Sosnin

IPC: H04W72/04 ,  H04W76/14 ,  H04L1/16 ,  H04W72/12

Abstract: Embodiments of the present disclosure describe apparatuses and methods for selecting or extending time resource patterns relating to device-to-device (D2D) functionality. Various embodiments may include processing circuitry to select a subset of a predefined set of D2D time resource pattern bitmaps and generate a signal having information corresponding to the selected subset of D2D time resource pattern bitmaps. Other embodiments may be described and/or claimed.

公开(公告)号：US09888471B2

公开(公告)日：2018-02-06

申请号：US14671315

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Sergey Panteleev ,  Alexey Khoryaev ,  Debdeep Chatterjee ,  Sergey Sosnin

IPC: H04W72/04 ,  H04L1/16 ,  H04W76/02 ,  H04W72/12

CPC classification number: H04W72/0446 ,  H04L1/1614 ,  H04W72/1289 ,  H04W76/14

Abstract: Embodiments of the present disclosure describe apparatuses and methods for selecting or extending time resource patterns relating to device-to-device (D2D) functionality. Various embodiments may include processing circuitry to select a subset of a predefined set of D2D time resource pattern bitmaps and generate a signal having information corresponding to the selected subset of D2D time resource pattern bitmaps. Other embodiments may be described and/or claimed.

公开(公告)号：US09706591B2

公开(公告)日：2017-07-11

申请号：US14701423

申请日：2015-04-30

Applicant: Intel Corporation

Inventor： Sergey Panteleev ,  Alexey Khoryaev ,  Debdeep Chatterjee ,  Sergey Sosnin

IPC: H04W4/00 ,  H04W76/02 ,  H04W72/12 ,  H04W76/06 ,  H04W8/00

CPC classification number: H04W76/14 ,  H04W8/005 ,  H04W72/121 ,  H04W76/34

Abstract: In embodiments, apparatuses, methods, and storage media may be described for mapping media access control (MAC) protocol data units (PDUs) that are used to transmit scheduling assignment (SA) discovery, and/or device-to-device (D2D) data. Embodiments herein may describe how one or more MAC PDUs may be mapped into a time resource pattern for transmissions (T-RPT). Embodiments herein may further describe examples of how and when a UE may skip subframes in transmissions of the SA and/or data. Additionally, embodiments herein may further describe examples of how a UE may behave if the UE cannot transmit one or more scheduled instances of SA or data. Additionally, embodiments herein may describe resolution of collisions of D2D discovery messages in the time domain. Other embodiments may be described and/or claimed.

公开(公告)号：US09294230B2

公开(公告)日：2016-03-22

申请号：US13934095

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Seunghee Han ,  Hong He ,  Jong-Kae Fwu ,  Shafi Bashar ,  Debdeep Chatterjee ,  Youn Hyoung Heo

IPC: H04L1/16 ,  H04L1/18

CPC classification number: H04W72/0413 ,  H04L1/1657 ,  H04L1/1671 ,  H04L1/1861 ,  H04L5/0055 ,  H04L5/0057 ,  H04L5/14 ,  H04W72/0446 ,  H04W72/1268 ,  Y02D70/126

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for multiplexing channel state information and hybrid automatic repeat request-acknowledgement information. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例描述了用于复用信道状态信息和混合自动重传请求确认信息的设备，方法，计算机可读介质和系统配置。 可以描述和要求保护其他实施例。

公开(公告)号：US09154279B2

公开(公告)日：2015-10-06

申请号：US14543759

申请日：2014-11-17

Applicant: Intel Corporation

Inventor： Debdeep Chatterjee ,  Kamran Etemad ,  Rongzhen Yang ,  Jong-Kae Fwu ,  Apostolos Papathanassiou

IPC: H04W72/04 ,  H04L5/00 ,  H04W72/08 ,  H04B7/02 ,  H04B7/04 ,  H04B7/06 ,  H04W4/00 ,  H04W4/08

CPC classification number: H04W72/044 ,  H04B1/69 ,  H04B7/024 ,  H04B7/0413 ,  H04B7/0456 ,  H04B7/0617 ,  H04B7/0623 ,  H04B7/0626 ,  H04B7/0639 ,  H04L1/0026 ,  H04L1/0027 ,  H04L1/0031 ,  H04L1/1864 ,  H04L1/1887 ,  H04L1/1896 ,  H04L5/0035 ,  H04L5/0048 ,  H04L5/005 ,  H04L5/0053 ,  H04L5/1469 ,  H04L12/189 ,  H04L27/2607 ,  H04L65/4076 ,  H04L65/608 ,  H04W4/08 ,  H04W4/70 ,  H04W36/0094 ,  H04W36/04 ,  H04W48/16 ,  H04W52/0216 ,  H04W72/04 ,  H04W72/0406 ,  H04W72/042 ,  H04W72/0493 ,  H04W72/082 ,  H04W72/085 ,  H04W76/27 ,  H04W76/28 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1224 ,  Y02D70/1242 ,  Y02D70/1244 ,  Y02D70/1246 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/164 ,  Y02D70/166 ,  Y02D70/168 ,  Y02D70/21 ,  Y02D70/22 ,  Y02D70/23 ,  Y02D70/24 ,  Y02D70/442 ,  Y02D70/444

Abstract: Disclosed embodiments may include an apparatus having one or more processors coupled to one or more computer-readable storage media. The one or more processors may be configured to transmit and/or receive channel state information reference signal (CSI-RS) resource configuration information, demodulation reference signals (DM-RS), uplink sounding reference signals (SRS), and power control parameters to support uplink coordinated multi-point (CoMP) operations. Other embodiments may be disclosed.

Abstract translation: 公开的实施例可以包括具有耦合到一个或多个计算机可读存储介质的一个或多个处理器的装置。 一个或多个处理器可以被配置为将信道状态信息参考信号（CSI-RS）资源配置信息，解调参考信号（DM-RS），上行链路探测参考信号（SRS）和功率控制参数发送和/或接收到 支持上行协调多点（CoMP）操作。 可以公开其他实施例。

公开(公告)号：US09088977B2

公开(公告)日：2015-07-21

申请号：US13853390

申请日：2013-03-29

Applicant: Intel Corporation

Inventor： Hong He ,  Jong-Kae Fwu ,  Debdeep Chatterjee ,  Rui Huang

IPC: H04W4/00 ,  H04W72/04 ,  H04L12/807 ,  H04W28/12 ,  H04L1/18 ,  H04L5/00 ,  H04L1/16 ,  H04L5/14

CPC classification number: H04W72/0406 ,  H04L1/1607 ,  H04L1/18 ,  H04L1/1812 ,  H04L1/1887 ,  H04L5/00 ,  H04L5/001 ,  H04L5/0055 ,  H04L5/1469 ,  H04L47/27 ,  H04W28/12 ,  Y02D70/126 ,  Y02E40/62

Abstract: Technology to support Hybrid Automatic Retransmission re-Quest (HARQ) for Carrier Aggregation (CA) is disclosed. For example, a device, at a processor residing on a User Equipment (UE), includes a sizing module and a window module. The sizing module can be configured to determine a first size of a first bundling window for a first Component Carrier (CC) and a second size of a second bundling window for a second CC. The window module can be configured to: generate a first virtual window comprising a selected number of DownLink (DL) sub-frames in the first bundling window that are added to DL sub-frames in the second bundling window; and generate a second virtual window comprising remaining DL sub-frames from the first bundling window that are not added to the first virtual window. The selected number of DL sub-frames can be proportional to a difference between the first size and the second size.

Abstract translation: 公开了支持用于载波聚合（CA）的混合自动重传任务（HARQ）技术。 例如，驻留在用户设备（UE）上的处理器处的设备包括大小调整模块和窗口模块。 尺寸模块可以被配置为确定用于第一分量载波（CC）的第一捆绑窗口的第一尺寸和用于第二CC的第二捆绑窗口的第二尺寸。 窗口模块可以被配置为：生成第一虚拟窗口，该第一虚拟窗口包括在第二绑定窗口中添加到DL子帧的第一绑定窗口中的选定数量的下行链路（DL）子帧; 并且生成包括未添加到第一虚拟窗口的来自第一捆绑窗口的剩余DL子帧的第二虚拟窗口。 所选数量的DL子帧可以与第一大小和第二大小之间的差成比例。

公开(公告)号：US20250142566A1

公开(公告)日：2025-05-01

申请号：US18835408

申请日：2023-04-19

Applicant: Intel Corporation

Inventor： Yingyang Li ,  Yi Wang Wang ,  Gang Xiong ,  Debdeep Chatterjee

IPC: H04W72/1273 ,  H04W72/0446 ,  H04W72/51 ,  H04W72/566

Abstract: A UE configured for operating in a 5G NR network may decode signalling that schedules two physical downlink shared channels (PDSCHs) in a same time slot. When the UE is a reduced-bandwidth (RBW) reduced-capacity (RedCap) UE (RBW-RedCap UE), the UE may determine if a total number of allocated PRBs in an OFDM symbol for the two scheduled PDSCHs exceed a predetermined value when the two scheduled PDSCHs either partially or fully overlap in time in non-overlapping PRBs. The UE may also prioritize decoding of one of the two scheduled PDSCHs when the total number of allocated PRBs exceed the predetermined value and when the two scheduled PDSCHs either partially or fully overlap in time in non-overlapping PRBs. If a first of the two scheduled PDSCHs is a unicast PDSCH and a second of the two scheduled PDSCHs is a broadcast PDSCH, the UE may prioritize decoding of the unicast PDSCH.