公开(公告)号：US20200279937A1

公开(公告)日：2020-09-03

申请号：US16645962

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Kanwaljit Singh ,  Nicole K. Thomas ,  Hubert C. George ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Payam Amin ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/43 ,  H01L29/12 ,  H01L29/165 ,  G06N10/00 ,  H01L29/423 ,  H01L27/088

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.

公开(公告)号：US10714604B2

公开(公告)日：2020-07-14

申请号：US16017031

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Hubert C. George ,  David J. Michalak ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66 ,  H01L29/15 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/12 ,  G06N10/00 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/76 ,  H01L29/423 ,  H01L21/308 ,  H01L29/51 ,  H01L29/43 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US10593756B2

公开(公告)日：2020-03-17

申请号：US16314779

申请日：2016-08-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Jeanette M. Roberts ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/12 ,  H01L29/82 ,  B82Y10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of first gates disposed above the quantum well stack, wherein at least two of the first gates are spaced apart in a first dimension above the quantum well stack, at least two of the first gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and a second gate disposed above the quantum well stack, wherein the second gate extends between at least two of the first gates spaced apart in the first dimension, and the second gate extends between at least two of the first gates spaced apart in the second dimension.

公开(公告)号：US20190305038A1

公开(公告)日：2019-10-03

申请号：US16307979

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： David J. Michalak ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/22 ,  H01L23/522 ,  H01L39/02 ,  H01L39/24 ,  H01L23/66 ,  G06N10/00

Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190267692A1

公开(公告)日：2019-08-29

申请号：US16320203

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Stefano Pellerano

IPC: H01P3/08 ,  H01P11/00 ,  G06N10/00

Abstract: Described herein are new transmission line structures for use as resonators and non-resonant interconnects in quantum circuits. In one aspect of the present disclosure, a proposed structure includes a substrate, a ground plane disposed over the substrate, a dielectric layer disposed over the ground plane, and a conductor strip disposed over the dielectric layer. In another aspect, a proposed structure includes a substrate, a lower ground plane disposed over the substrate, a lower dielectric layer disposed over the lower ground plane, a conductor strip disposed over the lower dielectric layer, an upper dielectric layer disposed over the conductor strip, and an upper ground plane disposed over the upper dielectric layer. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits. Methods for fabricating such structures are disclosed as well.

公开(公告)号：US20190044050A1

公开(公告)日：2019-02-07

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/04 ,  H01L39/24 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US20190043974A1

公开(公告)日：2019-02-07

申请号：US15900655

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  James S. Clarke ,  Willy Rachmady

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a layer of gate dielectric above the quantum well stack; a first gate metal and a second gate metal above the layer of gate dielectric; and a gate wall between the first gate metal and the second gate metal, wherein the gate wall is above the layer of gate dielectric, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material.

公开(公告)号：US20190042968A1

公开(公告)日：2019-02-07

申请号：US16013384

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N99/00 ,  B82Y10/00 ,  H01L27/18 ,  H01L39/22 ,  H03K19/195

Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.

公开(公告)号：US20190042967A1

公开(公告)日：2019-02-07

申请号：US16011812

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  Roman Caudillo ,  Ravi Pillarisetty ,  Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: G06N99/00 ,  H03K19/195 ,  H03K17/92 ,  H01L27/18 ,  B82Y10/00

CPC classification number: G06N10/00 ,  B82Y10/00 ,  G11C11/44 ,  H01L27/18 ,  H01L29/66439 ,  H01L29/66977 ,  H01L39/223 ,  H01L39/2493 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H03K17/92 ,  H03K19/1952

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

公开(公告)号：US20250107221A1

公开(公告)日：2025-03-27

申请号：US18969844

申请日：2024-12-05

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778 ,  H10N69/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.