公开(公告)号：US09123600B2

公开(公告)日：2015-09-01

申请号：US13778654

申请日：2013-02-27

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni ,  Ilyas Mohammed

IPC: H01L21/00 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/525 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.

Abstract translation: 芯片封装具有多个芯片，可以并排布置或以交错的台阶布置布置。 芯片的触点连接到芯片本身或再分布基板上承载的互连焊盘。 互连焊盘理想地布置在相对窄的互连区域中，使得互连焊盘可以容易地线接合或以其他方式连接到封装衬底。

公开(公告)号：US09123555B2

公开(公告)日：2015-09-01

申请号：US14063119

申请日：2013-10-25

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/50 ,  H01L24/06 ,  H01L24/09 ,  H01L2224/023 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/09151 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/14361 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0248 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3415 ,  H05K2201/10159 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.

Abstract translation: 微电子封装具有带有第一和第二平行孔的电介质元件。 第一微电子元件具有覆盖第一孔的触点，并且第二微电子元件具有覆盖第二孔的触点。 第二微电子元件可以覆盖第一微电子元件的后表面和与第一微电子元件相同的介质元件的表面。 位于所述第一和第二孔之间的电介质元件的第二表面上的第一端子可被配置为承载用于对第一和第二微电子元件内的存储器位置的读取和写入访问的所有数据信号。

公开(公告)号：US20150115434A1

公开(公告)日：2015-04-30

申请号：US14585390

申请日：2014-12-30

Applicant: Invensas Corporation

Inventor： Wael Zohni

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L23/3672 ,  H01L23/433 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate.

Abstract translation: 微电子封装包括衬底，第一和第二微电子元件以及散热器。 衬底具有端子，其上配置有与封装外部的部件电连接。 第一微电子元件与衬底相邻，并且第二微电子元件至少部分地覆盖第一微电子元件。 散热器是片状的，分离第一和第二微电子元件，并且包括孔。 连接延伸穿过孔并将第二微电子元件与衬底电耦合。

公开(公告)号：US20150076714A1

公开(公告)日：2015-03-19

申请号：US14027571

申请日：2013-09-16

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC: H01L23/49 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/745 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13624 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/742 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00

Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Abstract translation: 微电子结构包括在第一表面具有导电元件的半导体。 线接合具有接合到导电元件和远离基座的自由端的基部，自由端远离基板和基部并且包括端面。 线接合限定其基端和端面之间的边缘表面。 顺应性材料层沿着线的第一部分中的边缘表面延伸，至少邻近其底部，并且填充引线接合的第一部分之间的空间，使得引线接合的第一部分通过顺应性 材料层。 线接合的第二部分由邻近端表面的端表面和边缘表面的部分限定，其从较柔性的第三表面延伸。

公开(公告)号：US08946901B2

公开(公告)日：2015-02-03

申请号：US13746571

申请日：2013-01-22

Applicant: Invensas Corporation

Inventor： Wael Zohni ,  Chung-Chuan Tseng

IPC: H01L23/13 ,  H01L21/58 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge.

Abstract translation: 微电子组件可以包括具有在基板的第一和第二相对面对的表面之间延伸的开口的基板，该开口在第一方向上伸长; 以及至少一个微电子元件，其具有面向并连接到所述基板的第一表面的正面和在所述开口的上方的前表面处的多个触点，所述微电子元件具有远离所述前表面延伸的第一和第二相对的周边边缘。 第一周边边缘在开口的内边缘延伸超过第一方向或与第一方向对齐，并且开口延伸超出第二周边边缘。

公开(公告)号：US08917532B2

公开(公告)日：2014-12-23

申请号：US13644012

申请日：2012-10-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni

IPC: G11C5/06 ,  H05K1/02 ,  G11C5/04 ,  H01L23/50 ,  H01L23/13 ,  H01L23/498 ,  H01L23/482 ,  H05K3/34 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  G11C5/04 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06156 ,  H01L2224/06164 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.

Abstract translation: 微电子封装包括具有覆盖衬底的第一表面的存储器阵列功能的微电子元件，所述微电子元件具有与衬底中的孔对准的多个触点。 配置为承载传送到封装的所有地址信号的第一端子可以暴露在第二衬底表面的第一区域内，第一区域设置在孔和衬底的周边边缘之间。 第一端子可以被配置为携带传送到封装的所有命令信号，存储体地址信号和命令信号，命令信号是写使能，行地址选通和列地址选通。

公开(公告)号：US20140362629A1

公开(公告)日：2014-12-11

申请号：US14075020

申请日：2013-11-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。

公开(公告)号：US08907500B2

公开(公告)日：2014-12-09

申请号：US13758412

申请日：2013-02-04

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/07

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/3736 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/07 ,  H01L2224/04042 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.

Abstract translation: 微电子封装可以包括具有在第一和第二横向方向上延伸的第一和第二相对表面的基板和在第一和第二表面之间延伸的开口，并且限定第一和第二不同部分，每个沿着沿着第一方向延伸的共同轴线延伸， 以及第二微电子元件，每个具有面向衬底的第一表面的前表面和在相应的前表面处的接触柱，在第二表面处暴露的多个端子以及与相应的第一和第二表面对准的第一和第二电连接 开口的部分并且从相应的第一和第二微电子元件的至少一些触点延伸到至少一些端子。 第一和第二微电子元件的接触柱可以与开口的相应的第一和第二部分对准。

公开(公告)号：US08848392B2

公开(公告)日：2014-09-30

申请号：US13840542

申请日：2013-03-15

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H05K1/11 ,  H05K1/14 ,  B81B7/00

CPC classification number: B81B7/007 ,  H01L23/5384 ,  H01L25/0652 ,  H01L2224/12105 ,  H01L2224/20

Abstract: A module is configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module includes a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts include first contacts having address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.

Abstract translation: 模块被配置为与具有端子和微电子元件的微电子组件连接。 该模块包括电路板承载导体，其被配置为承载命令和地址信息，共同支撑联接到导体的触点以及耦合到导体的模块触点。 共同支持触点包括具有以与第一类型的微电子组件连接的第一预定布置布置的地址和命令信息分配的第一触点，其中微电子元件被配置为通过第一触点对其耦合到其上的命令和地址信息进行采样 以及用于与第二类型的微电子组件连接的第二预定布置，其中微电子元件被配置为以大于第二采样率的第一采样率对第一触点的子集进行采样以对其进行采样，从而对与其耦合的命令和地址信息进行采样 第一个采样率。

公开(公告)号：US08786069B1

公开(公告)日：2014-07-22

申请号：US13898952

申请日：2013-05-21

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC: H01L23/498 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/49811 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include lower and upper package faces, lower terminals at the lower package face configured for connection with a first component, upper terminals at the upper package face configured for connection with a second component, first and second microelectronic elements each having memory storage array function, and conductive interconnects each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects can include first conductive interconnects configured to carry address information, signal assignments of a first set of the first interconnects having 180° rotational symmetry about a theoretical rotational axis with signal assignments of a second set of first interconnects. The conductive interconnects can also include second conductive interconnects configured to carry data information, the position of each second conductive interconnect having 180° rotational symmetry about the rotational axis with a position of a corresponding no-connect conductive interconnect.

Abstract translation: 微电子封装可以包括下封装面和上封装面，下封装面处的下端子被配置为与第一部件连接，上封装面上的上端子被配置为与第二元件连接，第一和第二微电子元件各自具有存储器 阵列功能和导电互连，每个电连接至少一个下端子与至少一个上端子。 导电互连可以包括被配置为承载地址信息的第一导电互连，具有关于第二组第一互连的信号分配的理论旋转轴线具有180°旋转对称性的第一组互连的第一组的信号分配。 导电互连还可以包括被配置为承载数据信息的第二导电互连，每个第二导电互连的位置具有相对于不连接导电互连的位置的围绕旋转轴线的180°旋转对称。