公开(公告)号：US20060060891A1

公开(公告)日：2006-03-23

申请号：US11231690

申请日：2005-09-21

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L27/148

CPC classification number: H01L24/97 ,  H01L23/04 ,  H01L23/24 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/16152 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract translation: 半导体封装具有固定在导电体中的浅开口中的变薄的半导体管芯。 模具底部的裸片电极被电镀有重新分布的接触件，该接触件与模具底部接触件重叠，并且绝缘体填充了模具和开口之间的环形间隙。 描述了用于制造包装的方法，其中引线框体中的多个间隔开的开口在工艺结束时被同时处理和分割。

公开(公告)号：US06858922B2

公开(公告)日：2005-02-22

申请号：US10050002

申请日：2002-01-15

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract translation: 用于两个或更多个半导体管芯的小尺寸封装包括第一和第二管芯，其安装在彼此垂直对准的引线框架焊盘的相对的相对表面上。 可以使用导电或绝缘粘合剂。 芯片可以是串联连接的相同的MOS器件，或者可以是一个功率管芯和用于控制功率管芯的第二个IC管芯。

公开(公告)号：US08390131B2

公开(公告)日：2013-03-05

申请号：US11890965

申请日：2007-08-08

Applicant: Sven Fuchs ,  Mark Pavier

Inventor： Sven Fuchs ,  Mark Pavier

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/30 ,  H01L23/3107 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2908 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73153 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0483 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/3651 ,  H01L2924/00

Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

Abstract translation: 一种半导体器件，其包括在电极上形成的一种材料的电极和具有较低电阻率的导电材料，以及制造该半导体器件的工艺。

公开(公告)号：US08089147B2

公开(公告)日：2012-01-03

申请号：US11591834

申请日：2006-11-02

Applicant: Mark Pavier ,  David Bushnell

Inventor： Mark Pavier ,  David Bushnell

IPC: H01L23/34

CPC classification number: H01L25/162 ,  H01L25/072 ,  H01L2224/73153 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract translation: 绝缘金属衬底复合材料在一个表面上具有图案化的导电层，并且在图案化区段上接收通向IMS边缘的一个或多个MOSFET电极或其它管芯。 IMS的外围被杯形或弯曲以形成一个浅的罐，其中两个或多个管芯被固定并且热耦合到罐的扁平腹板上，而与模具表面热耦合的模具表面上的电极可以导致端子 罐的边缘与模具的底表面共面。 电极可以在外部或内部连接以形成半桥电路。

公开(公告)号：US07678609B2

公开(公告)日：2010-03-16

申请号：US11592408

申请日：2006-11-03

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/97 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/73153 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  Y10T436/19 ,  Y10T436/20 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package which includes coupling an electrode of a semiconductor device to a portion of a lead frame, overmolding at least a portion of the die, and then removing a portion of the die to obtain a desired thickness.

Abstract translation: 一种制造半导体封装的方法，包括将半导体器件的电极耦合到引线框架的一部分，包覆模制至少一部分模具，然后去除模具的一部分以获得期望的厚度。

公开(公告)号：US07382051B2

公开(公告)日：2008-06-03

申请号：US11153097

申请日：2005-06-15

Applicant: Sven Fuchs ,  Mark Pavier

Inventor： Sven Fuchs ,  Mark Pavier

IPC: H01L23/48

CPC classification number: H01L23/10 ,  H01L23/041 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

公开(公告)号：US07365423B2

公开(公告)日：2008-04-29

申请号：US11788584

申请日：2007-04-20

Applicant: Mark Pavier

Inventor： Mark Pavier

IPC: H01L23/043

CPC classification number: H01L24/97 ,  H01L23/04 ,  H01L23/24 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73153 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2924/16152 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Abstract translation: 半导体封装具有固定在导电体中的浅开口中的变薄的半导体管芯。 模具底部的裸片电极被电镀有重新分布的接触件，该接触件与模具底部接触件重叠，并且绝缘体填充了模具和开口之间的环形间隙。 描述了用于制造包装的方法，其中引线框体中的多个间隔开的开口在工艺结束时被同时处理和分割。

公开(公告)号：US20060261473A1

公开(公告)日：2006-11-23

申请号：US11409679

申请日：2006-04-24

Applicant: Norman Connah ,  Mark Pavier ,  Phillip Adamson ,  Hazel Schofield

Inventor： Norman Connah ,  Mark Pavier ,  Phillip Adamson ,  Hazel Schofield

IPC: H01L23/34

CPC classification number: H01L23/49527 ,  H01L23/15 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/4951 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48744 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73255 ,  H01L2224/85207 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

Abstract translation: 半导体器件封装包括具有一个或多个焊盘的衬底和至少一个半导体器件，其具有电连接到衬底焊盘的一个或多个电极。 封装还包括与衬底焊盘电连接的一个或多个端子，并且提供与设备的外部连接。

公开(公告)号：US20060249836A1

公开(公告)日：2006-11-09

申请号：US11409298

申请日：2006-04-21

Applicant: Andy Farlow ,  Mark Pavier ,  Andrew Sawle ,  George Pearson ,  Martin Standing

Inventor： Andy Farlow ,  Mark Pavier ,  Andrew Sawle ,  George Pearson ,  Martin Standing

IPC: H01L23/34

CPC classification number: H01L24/33 ,  H01L23/041 ,  H01L23/492 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2224/83801 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/30105 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.

公开(公告)号：US07095099B2

公开(公告)日：2006-08-22

申请号：US10988443

申请日：2004-11-12

Applicant: Stephen Oliver ,  Marco Soldano ,  Mark Pavier ,  Glyn Connah ,  Ajit Dubhashi

Inventor： Stephen Oliver ,  Marco Soldano ,  Mark Pavier ,  Glyn Connah ,  Ajit Dubhashi

IPC: H01L23/495

CPC classification number: H01L24/06 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48747 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85207 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A low profile semiconductor device package includes a lead frame with terminal leads and two die pads for receiving at least two semiconductor die that are interconnected to form a circuit. A further low profile semiconductor device package includes a lead frame with two die pads for receiving at least two semiconductor die that are interconnected to form a circuit and also has a reduced height through removal of a mounting tab. An example of such device packages is a package that includes first and second MOSFET die, each connected to a respective die pad. The source of one MOSFET is connected to the drain of the other MOSFET, thereby forming a low profile device package that provides a half-bridge circuit. Other example device packages include different arrangements of two interconnected MOSFET die, two interconnected IGBTs, or a combination of a MOSFET die and a diode.

Abstract translation: 低剖面半导体器件封装包括具有端子引线的引线框架和用于接收互连以形成电路的至少两个半导体管芯的两个管芯焊盘。 进一步的低调半导体器件封装包括具有两个管芯焊盘的引线框架，用于接收至少两个互连以形成电路的半导体管芯，并且还通过移除安装突片而具有减小的高度。 这种器件封装的示例是包括第一和第二MOSFET管芯的封装，每个MOSFET管芯连接到相应的管芯焊盘。 一个MOSFET的源极连接到另一个MOSFET的漏极，从而形成提供半桥电路的低剖面器件封装。 其他示例性器件封装包括两个互连的MOSFET管芯，两个互连的IGBT或MOSFET管芯和二极管的组合的不同布置。