中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

49 records (took 0.021 seconds)

    Memory Cells Comprising Ferroelectric Material And Including Current Leakage Paths Having Different Total Resistances
    41.
    发明申请
    Memory Cells Comprising Ferroelectric Material And Including Current Leakage Paths Having Different Total Resistances 审中-公开

    公开(公告)号：US20200279907A1

    公开(公告)日：2020-09-03

    申请号：US16874845

    申请日：2020-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L49/02 ,  H01L27/11507

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

    Memory cells comprising ferroelectric material and including current leakage paths having different total resistances
    42.
    发明授权
    Memory cells comprising ferroelectric material and including current leakage paths having different total resistances 有权

    公开(公告)号：US10396145B2

    公开(公告)日：2019-08-27

    申请号：US15404576

    申请日：2017-01-12

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L49/02

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

    Resistive memory devices
    44.
    发明授权
    Resistive memory devices 有权

    公开(公告)号：US10090462B2

    公开(公告)日：2018-10-02

    申请号：US14960953

    申请日：2015-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Durai Vishak Nirmal Ramaswamy ,  Lei Bi ,  Beth R. Cook ,  Dale W. Collins

    IPC: H01L45/00 ,  H01L27/24 ,  H01L21/02 ,  G11C13/00

    Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.

    Memory cells
    47.
    发明授权
    Memory cells 有权
    记忆单元

    公开(公告)号：US09431606B1

    公开(公告)日：2016-08-30

    申请号：US14825087

    申请日：2015-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Durai Vishak Nirmal Ramaswamy ,  Dale W. Collins ,  Christopher W. Petz ,  Beth R. Cook

    IPC: H01L45/00

    CPC classification number: H01L45/1266 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/14

    Abstract: Some embodiments include a memory cell having a pair of electrodes, and a plurality of switching levels between the electrodes. Each switching level has an ion buffer region and a dielectric region. At least one switching level differs from another switching level in one or both of thickness and composition of the ion buffer region and/or the dielectric region.

    Abstract translation: 一些实施例包括具有一对电极的存储单元和电极之间的多个开关电平。 每个开关电平具有离子缓冲区和电介质区。 至少一个开关电平与离子缓冲区域和/或电介质区域的厚度和组成中的一个或两个中的另一个开关电平不同。

Patent Agency Ranking