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41.发明授权公开(公告)号：US11068336B2
公开(公告)日：2021-07-20
申请号：US16510591
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Juane Li , Fangfang Zhu
Abstract: A request to store a first data is received. The first data and a first error-checking data are received. The first error-checking data can be based on a cyclic redundancy check (CRC) operation of the first data. A second data is generated by modifying the first data. A second error-checking data of the second data is generated by using the first error-checking data and a difference between the first data and the second data.
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42.发明授权公开(公告)号：US10891224B2
公开(公告)日：2021-01-12
申请号：US16123979
申请日：2018-09-06
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Ying Yu Tai
Abstract: A determination is made that a source group of data management units of a memory component satisfies a threshold wear condition. A wear leveling operation is performed by copying data from a first data management unit of the source group of data management units to a second data management unit of a destination group of data management units of the memory component. A logical address of the first data management unit is determined. Indicators in a mapping data structure are moved from entries associated with the first data management unit to another entries in the mapping data structure that are subsequent to the entries associated with the first data management unit. The indicators are used to access data requested by a host system at the source group of data management units or at the destination group of data management units.
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公开(公告)号：US10860219B2
公开(公告)日：2020-12-08
申请号：US16153016
申请日：2018-10-05
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Jiangli Zhu , Ning Chen , Ying Yu Tai
Abstract: Data is copied, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first set of groups of data blocks that are not mapped to include the first group of data blocks in the second set of groups of data blocks that are mapped. A sub-total write counter associated with the first group of data blocks is reset. A value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the first group of data blocks has been included in the second set of groups of data blocks. A wear leveling operation is performed on the first group of data blocks based on the sub-total write counter.
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公开(公告)号：US10761739B2
公开(公告)日：2020-09-01
申请号：US16110739
申请日：2018-08-23
Applicant: Micron Technology, Inc.
Inventor： Ying Yu Tai , Ning Chen , Jiangli Zhu
Abstract: A memory sub-system performs a first wear leveling operation among a plurality of individual data units of the memory component after a first interval and performs a second wear leveling operation among a first plurality of groups of data units of the memory component after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units. The memory sub-system further performs a third wear leveling operation among a second plurality of groups of data units of the memory component after a third interval, wherein a second group of the second plurality of groups comprises the first plurality of groups of data units.
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公开(公告)号：US20250156101A1
公开(公告)日：2025-05-15
申请号：US19023021
申请日：2025-01-15
Applicant: Micron Technology, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu , Ning Chen
IPC: G06F3/06
Abstract: A memory sub-system periodically performs a first wear leveling operation using a direct mapping function on a data management unit of a memory component in the memory sub-system at a first frequency. The memory sub-system further periodically performs a second wear leveling operation using indirect mapping on a group of data management units of the memory component at a second frequency, wherein the second wear leveling operation is performed less frequently than the first wear leveling operation.
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Patent Agency Ranking
公开(公告)号：US12189960B2
公开(公告)日：2025-01-07
申请号：US17954023
申请日：2022-09-27
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
Abstract: Embodiments include methods, systems, devices, instructions, and media for limiting hot-cold swap wear leveling in memory devices. In one embodiment, wear metric values are stored and monitored using multiple wear leveling criteria. The multiple wear leveling criteria include a hot-cold swap wear leveling criteria, which may make use of a write count offset value. Based on a first wear metric value of a first management group and a second wear metric value of a second management group, the first management group and the second management group are selected for a wear leveling swap operation. The wear leveling swap operation is performed with a whole management group read operation of the first management group to read a set of data, and a whole management group write operation to write the set of data to the second management group.
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公开(公告)号：US11789861B2
公开(公告)日：2023-10-17
申请号：US17742896
申请日：2022-05-12
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Ning Chen , Fangfang Zhu , Alex Tang
CPC classification number: G06F12/0246 , G06F11/3037 , G06F12/0292 , G11C16/349 , G06F2212/7211
Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.
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公开(公告)号：US11698867B2
公开(公告)日：2023-07-11
申请号：US17458173
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Fangfang Zhu , Juane Li , Jiangli Zhu , Ning Chen
IPC: G06F12/1009
CPC classification number: G06F12/1009 , G06F2212/7201
Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.
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公开(公告)号：US11681472B2
公开(公告)日：2023-06-20
申请号：US17492181
申请日：2021-10-01
Applicant: Micron Technology, Inc.
Inventor： Fangfang Zhu , Ying Yu Tai , Ning Chen , Jiangli Zhu , Alex Tang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F11/1004 , G06F13/1668
Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
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公开(公告)号：US20230069122A1
公开(公告)日：2023-03-02
申请号：US17458173
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Seungjune Jeon , Fangfang Zhu , Juane Li , Jiangli Zhu , Ning Chen
IPC: G06F12/1009
Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.
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