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    Through stack bridge bonding devices and associated methods
    42.
    发明授权
    Through stack bridge bonding devices and associated methods 有权

    公开(公告)号：US12237301B2

    公开(公告)日：2025-02-25

    申请号：US17750225

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

    WIRE BONDING FOR STACKED MEMORY DIES
    44.
    发明公开
    WIRE BONDING FOR STACKED MEMORY DIES 审中-公开

    公开(公告)号：US20240063168A1

    公开(公告)日：2024-02-22

    申请号：US17889170

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： See Hiong Leow ,  Hong Wan NG ,  Seng Kim Ye ,  Kelvin Aik Boo Tan ,  Ling Pan

    IPC: H01L23/00 ,  H01L27/105

    CPC classification number: H01L24/48 ,  H01L27/1052 ,  H01L2224/48105

    Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

    THREE DIMENSIONAL SEMICONDUCTOR TRACE LENGTH MATCHING AND ASSOCIATED SYSTEMS AND METHODS
    46.
    发明公开
    THREE DIMENSIONAL SEMICONDUCTOR TRACE LENGTH MATCHING AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20230378043A1

    公开(公告)日：2023-11-23

    申请号：US17750140

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4846

    Abstract: Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.

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