公开(公告)号：US06730589B2

公开(公告)日：2004-05-04

申请号：US10254600

申请日：2002-09-26

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2144

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract translation: 其封装尺寸接近其芯片尺寸的半导体器件具有应力吸收层，允许省略图案化的柔性衬底，并且允许同时制造多个部件。 存在：在晶片（10）上形成电极（12）的步骤; 在晶片（10）上设置作为应力消除层的树脂层（14）的步骤，避免电极（12）; 从所述树脂层（14）上的电极（12）形成作为布线的铬层（16）的步骤; 在所述树脂层（14）上方的所述铬层（16）上形成作为外部电极的焊球的步骤; 以及将晶片（10）切割成单独的半导体芯片的步骤; 在形成铬层（16）和焊球的步骤中，在晶片工艺中使用金属薄膜制造技术。

公开(公告)号：US06727595B2

公开(公告)日：2004-04-27

申请号：US10261630

申请日：2002-10-02

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2348

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L2224/73203 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: This is a semiconductor device, a method of the same, a circuit board, and a flexible substrate that are easy to handle, enable quality assurance, and also enable batch connection of a flexible substrate to the electrodes of a semiconductor chip. A gap preservation member 16 is provided on a surface, of a flexible substrate 12, on which connection portions 24 to electrodes 14 of a semiconductor chip 10 are disposed. The semiconductor chip 10 and the flexible substrate 12 are arranged in a state in which the gap preservation member 16 is interposed therebetween. The connection portions 24 provided on the flexible substrate 12 are connected to the electrodes 14 of the semiconductor chip 10, and a molding material is injected to provide a stress absorption layer 26.

Abstract translation: 这是一种易于处理的半导体器件，其方法，电路板和柔性基板，能够进行质量保证，并且还能够将柔性基板批量连接到半导体芯片的电极。 在柔性基板12的表面上设置有间隙保持部件16，半导体芯片10的连接部24〜电极14设置在该基板上。 半导体芯片10和柔性基板12配置成间隙保持部件16插入其间的状态。 设置在柔性基板12上的连接部分24连接到半导体芯片10的电极14，并且注入模塑材料以提供应力吸收层26。

公开(公告)号：US06642615B2

公开(公告)日：2003-11-04

申请号：US09793493

申请日：2001-02-27

Applicant: Nobuaki Hashimoto ,  Terunao Hanaoka

Inventor： Nobuaki Hashimoto ,  Terunao Hanaoka

IPC: H01L2304

CPC classification number: H01L24/12 ,  H01L21/288 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/9201 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07811 ,  H01L2924/10156 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a bump projecting from a first surface of a semiconductor chip; and forming a conductive layer so that part of the conductive layer is exposed at a position depressed from a second surface of the semiconductor chip opposite to the first surface, wherein the exposed part of the conductive layer and the bump become electrical connecting sections.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：形成从半导体芯片的第一表面突出的凸块; 以及形成导电层，使得所述导电层的一部分在与所述半导体芯片的与所述第一表面相反的第二表面凹陷的位置处露出，其中所述导电层和所述凸块的暴露部分变为电连接部。

公开(公告)号：US06627994B2

公开(公告)日：2003-09-30

申请号：US09908544

申请日：2001-07-20

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2348

CPC classification number: H01L24/86 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The present invention is a semiconductor device with improved adhesion properties of a resin with a wiring pattern, comprising a film fragment 14 having a patterned wiring pattern 16 including a projection 17, a semiconductor chip 12 having electrodes 13 bonded to the projection 17, and a resin 19 provided to the wiring pattern 16 in the region other than that of the projection 17; and the wiring pattern 16 has its surface of contact with the resin 19 roughened.

Abstract translation: 本发明是一种具有改进的具有布线图案的树脂的粘合性能的半导体器件，其包括具有包括突起17的图案化布线图案16的薄膜片段14，具有与突起17接合的电极13的半导体芯片12和 树脂19设置在与突起17不同的区域中的布线图案16上; 并且布线图案16具有与树脂19接触的表面粗糙化。

公开(公告)号：US06518651B2

公开(公告)日：2003-02-11

申请号：US09953858

申请日：2001-09-18

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23495

CPC classification number: H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

公开(公告)号：US06507095B1

公开(公告)日：2003-01-14

申请号：US09701138

申请日：2000-11-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23495

CPC classification number: H05K3/4084 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2203/0195 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wiring board comprises a substrate (10) in which an opening (14) is formed, a wiring pattern (20) formed on one surface of the substrate (10) and having a bent portion (22) intruding into the opening (14) and protruding from the other surface of the substrate (10), and a resin 26 with which an inside of the bent portion (22) is filled and allowing deformation to a certain degree while preventing large deformation, and the bent portion (22) forms the external terminals of the semiconductor device.

Abstract translation: 布线板包括其中形成有开口（14）的基板（10），形成在基板（10）的一个表面上并且具有侵入到开口（14）中的弯曲部分（22）的布线图案（20） 并且从基板（10）的另一个表面突出，并且在弯曲部分（22）的内部被填充并允许变形到一定程度同时防止大的变形的树脂26，并且弯曲部分（22）形成 半导体器件的外部端子。

公开(公告)号：US06475896B1

公开(公告)日：2002-11-05

申请号：US09117510

申请日：1999-04-22

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L2144

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract translation: 其封装尺寸接近其芯片尺寸的半导体器件具有应力吸收层，允许省略图案化的柔性衬底，并且允许同时制造多个部件。 存在：在晶片（10）上形成电极（12）的步骤; 在晶片（10）上设置作为应力消除层的树脂层（14）的步骤，避免电极（12）; 从所述树脂层（14）上的电极（12）形成作为布线的铬层（16）的步骤; 在所述树脂层（14）上方的所述铬层（16）上形成作为外部电极的焊球的步骤; 以及将晶片（10）切割成单独的半导体芯片的步骤; 在形成铬层（16）和焊球的步骤中，在晶片工艺中使用金属薄膜制造技术。

公开(公告)号：US06297964B1

公开(公告)日：2001-10-02

申请号：US09204548

申请日：1998-12-03

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K0118

CPC classification number: H01L24/50 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H05K1/0393 ,  H05K3/005 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/241 ,  H05K3/242 ,  H05K2203/1545 ,  H05K2203/175 ,  H01L2924/00

Abstract: A semiconductor device comprising an insulating film having a device hole, a plurality of bumps formed on the insulating film, a plurality of first leads having end faces thereof exposed on an outline edge of the insulating film, each of the first leads being electroplated and connected with one of the bumps, a plurality of second leads having end portions thereof protruding into the device hole, each of the second leads being electroplated and connected with one of the bumps, and a semiconductor chip connected with the end portions of the second leads in the device hole. The insulating film is outlined to have a cut in a region including each of the exposed end faces of the first leads.

Abstract translation: 一种半导体器件，包括具有器件孔的绝缘膜，在所述绝缘膜上形成的多个凸点，在所述绝缘膜的轮廓边缘上露出端面的多个第一引线，每个所述第一引线电镀并连接 其中一个凸块，多个第二引线的端部突出到器件孔中，每个第二引线电镀并与其中一个凸起连接，半导体芯片与第二引线的端部连接 设备孔。 轮廓的绝缘膜在包括第一引线的每个暴露的端面的区域中具有切口。

公开(公告)号：US06262473B1

公开(公告)日：2001-07-17

申请号：US09091127

申请日：1998-06-16

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23495

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/241 ,  H01L2924/00

Abstract: The invention relates to a semiconductor device formed by using a film carrier tape and having a package size that is close to the chip size, and also to a semiconductor device and a making method therefor which facilitates the injection of resin for sealing. A film carrier tape 32 comprises a plurality of connection leads (24); portions defining holes (29, 31) formed by punching out connection portions, where any one of the connection leads (24) are connected together, and by punching out an intersection portion; and portions defining rectangular holes (11, 15). Resin is injected through rectangular holes (11, 15), rectangular holes (12, 14) stop the spreading of the resin, and holes (29, 31) allow air to escape from the resin.

Abstract translation: 本发明涉及通过使用薄膜载带并且具有接近芯片尺寸的封装尺寸形成的半导体器件，以及一种有助于树脂密封注入的半导体器件及其制造方法。 薄膜载体带32包括多个连接引线（24）; 通过冲出连接部分形成的孔（29,31）的部分，其中连接引线（24）中的任何一个连接在一起，并且冲出交叉部分; 以及限定矩形孔（11,15）的部分。 树脂通过矩形孔（11,15）注入，矩形孔（12,14）阻止树脂的铺展，并且孔（29,31）允许空气从树脂中逸出。

公开(公告)号：US6057174A

公开(公告)日：2000-05-02

申请号：US220595

申请日：1998-12-28

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/60 ,  H01L23/36 ,  H01L23/495 ,  H01L23/498 ,  H01L21/44 ,  H01L21/326 ,  H01L21/479 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/86 ,  H01L23/36 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/7965 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: Method of fabricating semiconductor devices comprising the steps of: mounting a plurality of semiconductor chips on a film carrier tape; sealing each one of the semiconductor chips mounted on the film carrier type with epoxy resin; attaching an individual stiffener to the film carrier tape at a position corresponding to each one of the semiconductor chips; forming a plurality of bumps on the film carrier tape at a position corresponding to each one of the semiconductor chips; and punching out the film carrier tape into separate pieces of insulating film after above-described steps. In this method, each step is carried out on the film carrier tape running between supply and take-up reels.

Abstract translation: 制造半导体器件的方法包括以下步骤：将多个半导体芯片安装在薄膜载带上; 用环氧树脂密封安装在薄膜载体上的每个半导体芯片; 在与所述半导体芯片中的每一个对应的位置处将单独的加强件附接到所述胶片载带; 在与所述半导体芯片中的每一个相对应的位置处在所述胶片载带上形成多个凸起; 并且在上述步骤之后将薄膜载体带冲压成单独的绝缘薄片。 在这种方法中，每个步骤都是在供应卷取卷轴之间运行的胶片载带上执行的。