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公开(公告)号：US11409596B1
公开(公告)日：2022-08-09
申请号：US17184611
申请日：2021-02-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.
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公开(公告)号：US10782920B2
公开(公告)日：2020-09-22
申请号：US16186584
申请日：2018-11-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
IPC: G06F3/06
Abstract: A data access method, a memory storage apparatus and a memory control circuit unit are provided. The memory storage apparatus includes a rewritable non-volatile memory module and the memory control circuit unit for controlling the rewritable non-volatile memory module. The data access method includes: receiving an access command; detecting a temperature of the memory storage apparatus; determining whether the temperature of the memory storage apparatus is lower than a first threshold; if the temperature of the memory storage apparatus is lower than the first threshold, performing a dummy access command or adjusting an operating voltage. The data access method further includes performing the access command after the dummy access command is performed or the operating voltage is adjusted.
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公开(公告)号：US10678698B2
公开(公告)日：2020-06-09
申请号：US15706757
申请日：2017-09-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
IPC: G06F12/02 , G06F12/08 , G06F3/06 , G06F12/0884
Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.
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公开(公告)号：US20200073792A1
公开(公告)日：2020-03-05
申请号：US16168841
申请日：2018-10-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
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公开(公告)号：US20200065187A1
公开(公告)日：2020-02-27
申请号：US16153828
申请日：2018-10-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
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Patent Agency Ranking
公开(公告)号：US20190034329A1
公开(公告)日：2019-01-31
申请号：US15706765
申请日：2017-09-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
CPC classification number: G06F12/0246 , G06F3/0619 , G06F3/0631 , G06F3/0656 , G06F3/0679
Abstract: An exemplary embodiment of the disclosure provides a data storage method for a rewritable non-volatile memory module. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit of a first management unit and not storing the first data to the rewritable non-volatile memory module if a data content of the first data is identical to a data content of second data, and the second data is stored in the first physical unit; and storing logical-to-physical bit map information to a second physical unit in the first management unit, and the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit.
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公开(公告)号：US10152426B2
公开(公告)日：2018-12-11
申请号：US15183813
申请日：2016-06-16
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
IPC: G06F12/02 , G06F12/1009
Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.
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公开(公告)号：US10102121B1
公开(公告)日：2018-10-16
申请号：US15649655
申请日：2017-07-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: configuring a plurality of first type super physical units and at least one second type super physical unit, where one first type super physical unit includes at least two available physical erasing units which may be programmed simultaneously, and one second type super physical unit includes at least two available physical erasing units which may not be programmed simultaneously. The method also includes: configuring the first type super physical unit as to be programmed based on a first programming mode or a second programming mode, and configuring the second type super physical unit as to be programmed only based on the first programming mode.
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公开(公告)号：US10013187B2
公开(公告)日：2018-07-03
申请号：US14829648
申请日：2015-08-19
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679 , G06F12/0246 , G06F2212/7201
Abstract: A mapping table accessing method for a rewritable non-volatile memory module is provided. The method includes: storing a mapping record corresponding to a first physical erasing unit into the first physical erasing unit, wherein the mapping record of the first physical erasing unit is a mapping relation of physical programming units in the first physical erasing unit. The method further includes: storing a mapping record corresponding to a second physical erasing unit into the second physical erasing unit, wherein the mapping record of the second physical erasing unit is a mapping relation of physical programming units in the second physical erasing unit. A size of the mapping record of the first physical erasing unit is different from a size of the mapping record of the second physical erasing unit.
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公开(公告)号：US09773565B1
公开(公告)日：2017-09-26
申请号：US15458037
申请日：2017-03-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Chih-Kang Yeh
CPC classification number: G11C16/26 , G06F11/1048 , G06F11/1068 , G11C11/5642 , G11C16/32 , G11C29/021 , G11C29/028 , G11C29/52
Abstract: A memory retry-read method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a sequence of several retry-read parameter groups according to several weights of the retry-read parameter groups; reading data from a physical programming unit according to a read voltage; if the data are unable to be corrected by a corresponding ECC code, choosing an adjustment retry-read parameter group from the retry-read parameter groups; retrying reading new data from the physical programming unit according to the adjustment retry-read parameter group; if the new data are able to be corrected by the corresponding ECC code, determining the adjustment retry-read parameter group to be an available retry-read parameter group; and adjusting the weight of the available retry-read parameter group.
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