公开(公告)号：US11652088B2

公开(公告)日：2023-05-16

申请号：US17452824

申请日：2021-10-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  SungSoo Kim ,  HeeSoo Lee

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L23/538 ,  H01L23/552 ,  H01L24/11 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/1134 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/03

Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

公开(公告)号：US20220359418A1

公开(公告)日：2022-11-10

申请号：US17307727

申请日：2021-05-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim ,  HeeSoo Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/16 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00

Abstract: An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

公开(公告)号：US11244908B2

公开(公告)日：2022-02-08

申请号：US16181619

申请日：2018-11-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  Deokkyung Yang ,  HeeSoo Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.

公开(公告)号：US11189598B2

公开(公告)日：2021-11-30

申请号：US16570165

申请日：2019-09-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  SungSoo Kim ,  HeeSoo Lee

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and second semiconductor component between the first substrate and second substrate. A first encapsulant is deposited between the first substrate and second substrate. A SiP submodule is disposed over the first substrate or second substrate opposite the encapsulant. A shielding layer is formed over the SiP submodule.

公开(公告)号：US20210151386A1

公开(公告)日：2021-05-20

申请号：US17163776

申请日：2021-02-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L23/66

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US20200219835A1

公开(公告)日：2020-07-09

申请号：US16821093

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  OhHan Kim ,  HeeSoo Lee ,  DaeHyeok Ha ,  Wanil Lee

IPC: H01L23/00 ,  H01L23/538

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

公开(公告)号：US12266614B2

公开(公告)日：2025-04-01

申请号：US18155878

申请日：2023-01-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  HeeSoo Lee ,  Wanil Lee ,  SangDuk Lee

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.

公开(公告)号：US20240321768A1

公开(公告)日：2024-09-26

申请号：US18188720

申请日：2023-03-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HeeYoun Kim

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/29 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2924/186 ,  H01L2924/3025

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

公开(公告)号：US20240096736A1

公开(公告)日：2024-03-21

申请号：US17932987

申请日：2022-09-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HyunSeok Park

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/3733 ,  H01L21/4882 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3737 ,  H01L25/165 ,  H01L24/16

Abstract: A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.

公开(公告)号：US20240014093A1

公开(公告)日：2024-01-11

申请号：US17810901

申请日：2022-07-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  OMin Kwon ,  HeeSoo Lee

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/433

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/4334

Abstract: A semiconductor device has a first substrate and electrical component disposed over the first substrate. A graphene layer is disposed over the electrical component, and a thermal interface material is disposed between the graphene layer. A heat sink is disposed over the thermal interface material. The graphene layer, in combination with the thermal interface material, aids with the heat transfer between the electrical component and heat sink. The graphene layer may be disposed over a second substrate made of copper. An encapsulant is deposited over the first substrate and around the electrical component and graphene substrate. The thermal interface material and heat sink may extend over the encapsulant. The heat sink can have vertical or angled extensions from the horizontal portion of the heat sink down to the substrate. The heat sink can extend over multiple modules.