公开(公告)号：US20230154812A1

公开(公告)日：2023-05-18

申请号：US18154993

申请日：2023-01-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/66 ,  H01L23/60

CPC classification number: H01L23/31 ,  H01L21/565 ,  H01L23/66 ,  H01L23/60

Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

公开(公告)号：US11616025B2

公开(公告)日：2023-03-28

申请号：US17126621

申请日：2020-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L21/033 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

公开(公告)号：US11610847B2

公开(公告)日：2023-03-21

申请号：US17314916

申请日：2021-05-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  SeongHwan Park ,  JinHee Jung

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L21/48 ,  H01Q1/22

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

公开(公告)号：US11581233B2

公开(公告)日：2023-02-14

申请号：US17307795

申请日：2021-05-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim

IPC: H01L23/31 ,  H01L23/60 ,  H01L23/66 ,  H01L21/56

Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

公开(公告)号：US20220367381A1

公开(公告)日：2022-11-17

申请号：US17317082

申请日：2021-05-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H05K1/02 ,  H01L21/56 ,  H01L23/532

Abstract: A semiconductor device has a substrate and electrical components disposed over the substrate. An encapsulant is disposed over the substrate and electrical components. A multi-layer shielding structure is formed over the encapsulant. The multi-layer shielding structure has a first layer of ferromagnetic material and second layer of a protective layer or conductive layer. The ferromagnetic material can be iron, nickel, nickel iron alloy, iron silicon alloy, silicon steel, nickel iron molybdenum alloy, nickel iron molybdenum copper alloy, iron silicon aluminum alloy, nickel zinc, manganese zinc, other ferrites, amorphous magnetic alloy, amorphous metal alloy, or nanocrystalline alloy. The first layer can be a single, homogeneous material. The protective layer can be stainless steel, tantalum, molybdenum, titanium, nickel, or chromium. The conductive layer can be copper, silver, gold, or aluminum. The multi-layer shielding structure protects the electrical components from low frequency and high frequency interference.

公开(公告)号：US20220359418A1

公开(公告)日：2022-11-10

申请号：US17307727

申请日：2021-05-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim ,  HeeSoo Lee

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/16 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00

Abstract: An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

公开(公告)号：US20220359321A1

公开(公告)日：2022-11-10

申请号：US17307795

申请日：2021-05-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim

IPC: H01L23/31 ,  H01L23/60 ,  H01L23/66 ,  H01L21/56

Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

公开(公告)号：US20220310408A1

公开(公告)日：2022-09-29

申请号：US17806924

申请日：2022-06-14

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L21/48 ,  H01L23/552 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L23/544

Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

公开(公告)号：US20190355695A1

公开(公告)日：2019-11-21

申请号：US16531593

申请日：2019-08-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  OhHan Kim ,  InSang Yoon

IPC: H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.

公开(公告)号：US20190172902A1

公开(公告)日：2019-06-06

申请号：US16267142

申请日：2019-02-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  HyungSang Park ,  SungSoo Kim

IPC: H01L49/02 ,  H05K1/18 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L28/40 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/185 ,  H05K3/4664 ,  H05K2201/10015

Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.