公开(公告)号：US11817153B2

公开(公告)日：2023-11-14

申请号：US17503197

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

公开(公告)号：US20230261024A1

公开(公告)日：2023-08-17

申请号：US18306006

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Euiyeol Kim ,  Hyounmin Baek ,  Jeong-Ho Lee ,  Youngwoo Chung ,  Heegeun Jeong

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14627 ,  H01L27/14689 ,  H01L27/14636 ,  H01L27/14603 ,  H01L27/14621

Abstract: An image sensor includes; a substrate having a first surface and an opposing second surface and including unit pixels respectively having photoelectric conversion regions, a semiconductor pattern disposed in a first trench defining the unit pixels, the semiconductor pattern including a first semiconductor layer provided on an inner surface of the first trench and a second semiconductor layer provided on the first semiconductor layer, and a first contact provided on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

公开(公告)号：US11670387B2

公开(公告)日：2023-06-06

申请号：US17328487

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin

IPC: G11C16/34 ,  G11C16/26 ,  G06N20/10 ,  G11C16/08 ,  G11C16/10 ,  G06F18/214

CPC classification number: G11C16/3481 ,  G06F18/214 ,  G06N20/10 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

公开(公告)号：US11610639B2

公开(公告)日：2023-03-21

申请号：US17336378

申请日：2021-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhyang Park ,  Jinyoung Kim ,  Jisang Lee ,  Sehwan Park ,  Ilhan Park

IPC: G11C16/26 ,  G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C16/04 ,  G11C29/12

Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.

公开(公告)号：US20220392930A1

公开(公告)日：2022-12-08

申请号：US17671651

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungeun Chang ,  Hyunchul Kim ,  Jinyoung Kim ,  Donghyun Kim ,  Sungin Kim

IPC: H01L27/146

Abstract: An image sensor includes: a substrate having a first surface on which light is incident and a second surface opposite to the first surface; a pixel isolation structure enclosing a pixel region in the substrate; a photoelectric conversion region in the pixel region; and a device isolation layer defining a pattern in the pixel region, wherein the device isolation layer includes a first portion contacting the pixel isolation structure and a second portion spaced apart from the pixel isolation structure, the device isolation layer extends from a second surface of the substrate into the substrate, and a length of the second portion of the device isolation layer in a vertical direction perpendicular to the first surface of the substrate is less than a length of the first portion of the device isolation layer in the vertical direction.

公开(公告)号：US11475972B2

公开(公告)日：2022-10-18

申请号：US17368460

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwi Yang ,  Ilhan Park ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10 ,  H03K19/21

Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.

公开(公告)号：US20220254419A1

公开(公告)日：2022-08-11

申请号：US17450871

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A memory system includes a non-volatile memory device including a machine learning (ML) module and a peripheral power management integrated circuit (IC), and a memory controller configured to command the non-volatile memory device to enter an idle mode by providing an external power command to the non-volatile memory device. The machine learning (ML) module configures a neural network and trains the neural network via machine learning, and the peripheral power management IC is configured to generate an internal power command that is different from the external power command based on the external power command and monitoring information corresponding to the ML module.

公开(公告)号：US11386974B2

公开(公告)日：2022-07-12

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C16/28 ,  G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18 ,  G11C29/12

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US20220214826A1

公开(公告)日：2022-07-07

申请号：US17376437

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeok Seo ,  Jinyoung Kim ,  Sehwan Park ,  Dongmin Shin ,  Woohyun Kang ,  Shinho Oh

IPC: G06F3/06 ,  G06N3/08

Abstract: A method of operating a nonvolatile memory device is provided. The method includes: dividing a memory block of a plurality of memory blocks provided in the nonvolatile memory device into a plurality of retention groups; generating time-difference information including a plurality of erase program interval (EPI) values corresponding to the plurality of retention groups; generating offset information including a plurality of offset values corresponding to differences between a plurality of default read voltages and a plurality of corrected read voltages; generating compensated read voltages corresponding to a read address based on the offset information and the time-difference information; and performing a read operation to read data from the nonvolatile memory device based on the read address and the compensated read voltages.

公开(公告)号：US11043268B2

公开(公告)日：2021-06-22

申请号：US16745823

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Jinyoung Kim ,  Junho Shin

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.