公开(公告)号：US20210104609A1

公开(公告)日：2021-04-08

申请号：US17060982

申请日：2020-10-01

Applicant: Tokyo Electron Limited

Inventor： Anton deVilliers ,  Jodi Grzeskowiak ,  Lars Liebmann ,  Daniel Chanemougame

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L27/12

Abstract: A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels.

公开(公告)号：US20210043630A1

公开(公告)日：2021-02-11

申请号：US16848366

申请日：2020-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers ,  Daniel Chanemougame

IPC: H01L27/108 ,  H01L27/092

Abstract: Aspects of the disclosure provide a semiconductor apparatus including a first stack of transistors and a second stack of transistors. The first stack includes a first transistor and a second transistor stacked on the first transistor along a Z direction perpendicular to a substrate plane. The second stack includes a third transistor and a fourth transistor stacked on the third transistor along the Z direction. The semiconductor apparatus includes a first routing track and a second routing track electrically isolated from the first routing track. The first and second routing tracks extend in an X direction parallel to the substrate plane. A first and fourth conductive trace conductively couple a first gate of the first transistor and a fourth gate of the fourth transistor to the first routing track, respectively. A first terminal structure conductively couples four source/drain terminals of the first, second, third and fourth transistors, respectively.

公开(公告)号：US20210043522A1

公开(公告)日：2021-02-11

申请号：US16848638

申请日：2020-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Daniel CHANEMOUGAME ,  Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other

公开(公告)号：US10770479B2

公开(公告)日：2020-09-08

申请号：US16357893

申请日：2019-03-19

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers ,  Kandabara Tapily ,  Jodi Grzeskowiak ,  Kai-Hung Yu

IPC: H01L27/118 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/768

Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.

公开(公告)号：US09997598B2

公开(公告)日：2018-06-12

申请号：US15671771

申请日：2017-08-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey Smith ,  Anton deVilliers ,  Nihar Mohanty ,  Subhadeep Kal ,  Kandabara Tapily

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L29/0676 ,  H01L21/823807 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device including a substrate and a gate region of a field effect transistor formed on the substrate. The gate region includes vertically stacked nanowires having longitudinal axes that extend parallel with a working surface of the substrate. A given stack of vertically stacked nanowires includes at least two nanowires vertically aligned in which a p-type nanowire and an n-type nanowire are spatially separated from each other vertically. The semiconductor device further includes a step-shaped connecting structure formed within the gate region that electrically connects each nanowire to positions above the gate region. A first gate electrode has a step-shaped profile and connects to a first-level nanowire.

公开(公告)号：US09263297B2

公开(公告)日：2016-02-16

申请号：US14605396

申请日：2015-01-26

Applicant: Tokyo Electron Limited

Inventor： Anton deVilliers

IPC: H01L21/44 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/308 ,  H01L21/02 ,  H01L21/033 ,  H01L21/314 ,  H01L21/311 ,  H01L27/108

CPC classification number: H01L21/32133 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/32139 ,  H01L27/108 ,  H01L2924/0002

Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.

Abstract translation: 公开了一种不需要原子层沉积技术的自对准双图案化方法。 技术包括使用阶梯蚀刻技术优先收缩一种材料而不收缩下层材料，接着是基于抗蚀剂的化学抛光和平面化技术，其产生足够物理支撑的变窄和突出的特征（单层厚度），并且 可以转移到一个或多个下层。 在去除抗蚀剂涂层之后，结果是在不使用ALD技术的情况下已被加倍的图案。 这种技术提高了用于自对准双重图案化的常规技术的效率。

公开(公告)号：US20150214070A1

公开(公告)日：2015-07-30

申请号：US14605396

申请日：2015-01-26

Applicant: Tokyo Electron Limited

Inventor： Anton deVilliers

IPC: H01L21/3213 ,  H01L21/308 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L21/32133 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/32139 ,  H01L27/108 ,  H01L2924/0002

Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.

Abstract translation: 公开了一种不需要原子层沉积技术的自对准双图案化方法。 技术包括使用阶梯蚀刻技术优先收缩一种材料而不收缩下层材料，接着是基于抗蚀剂的化学抛光和平面化技术，其产生足够物理支撑的变窄和突出的特征（单层厚度），并且 可以转移到一个或多个下层。 在去除抗蚀剂涂层之后，结果是在不使用ALD技术的情况下已被加倍的图案。 这种技术提高了用于自对准双重图案化的常规技术的效率。