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    Method of manufacturing a semiconductor apparatus having stacked devices
    42.
    发明授权
    Method of manufacturing a semiconductor apparatus having stacked devices 有权

    公开(公告)号：US12014984B2

    公开(公告)日：2024-06-18

    申请号：US17954953

    申请日：2022-09-28

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

    IPC: H01L23/528 ,  H01L21/768 ,  H01L25/07 ,  H01L27/092

    CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L23/5283 ,  H01L25/071 ,  H01L27/092

    Abstract: A method for forming a semiconductor apparatus includes forming a plurality of repetitive initial structures over a substrate of the semiconductor apparatus. An initial structure in the plurality of repetitive initial structures is formed by forming a first stack of transistors along a Z direction substantially perpendicular to a substrate plane, and forming local interconnect structures. Each of the transistors in the first stack of transistors is sandwiched between two of the local interconnect structures. Vertical conductive structures are formed substantially parallel to the Z direction, a height of one of the vertical conductive structures along the Z direction being at least a height of the initial structure. The initial structure is functionalized into a final structure by forming one or more connections each electrically coupling one of the local interconnect structures to one of the vertical conductive structures.

    Three-dimensional semiconductor device
    46.
    发明授权
    Three-dimensional semiconductor device 有权

    公开(公告)号：US11764266B2

    公开(公告)日：2023-09-19

    申请号：US18074684

    申请日：2022-12-05

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/1029 ,  H01L29/0665 ,  H01L29/66818 ,  H01L29/785

    Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

    Power distribution network for 3D logic and memory
    49.
    发明授权
    Power distribution network for 3D logic and memory 有权

    公开(公告)号：US11616020B2

    公开(公告)日：2023-03-28

    申请号：US17381449

    申请日：2021-07-21

    Applicant: Tokyo Electron Limited

    Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

    IPC: H01L23/528 ,  H01L29/08 ,  H01L25/065 ,  H01L27/11

    Abstract: A semiconductor device includes a transistor stack. The transistor stack has a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors includes a channel region stacked over the substrate and extending in a direction parallel to the substrate, a gate structure stacked over the substrate and surrounding the channel region of each of the plurality of transistors, and source/drain (S/D) regions stacked over the substrate and further positioned at two ends of the channel region of each of the plurality of transistors. The semiconductor device also includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack, and are electrically coupled to the transistor stack.

    CFET SRAM bit cell with three stacked device decks
    50.
    发明授权
    CFET SRAM bit cell with three stacked device decks 有权

    公开(公告)号：US11545497B2

    公开(公告)日：2023-01-03

    申请号：US17139303

    申请日：2020-12-31

    Applicant: Tokyo Electron Limited

    Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Jeffrey Smith

    IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

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