公开(公告)号：US20200043890A1

公开(公告)日：2020-02-06

申请号：US16152424

申请日：2018-10-05

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package structure is also provided.

公开(公告)号：US20170110393A1

公开(公告)日：2017-04-20

申请号：US15391861

申请日：2016-12-28

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Kai-Ming Yang ,  Wang-Hsiang Tsai ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/4673 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/10674 ,  Y10T29/49165 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.

公开(公告)号：US12266616B2

公开(公告)日：2025-04-01

申请号：US18470427

申请日：2023-09-20

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  John Hon-Shing Lau

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.

公开(公告)号：US12255279B2

公开(公告)日：2025-03-18

申请号：US17583222

申请日：2022-01-25

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang

IPC: H01L33/64 ,  H01L25/075 ,  H01L33/22 ,  H01L33/48 ,  H01L33/62

Abstract: A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.

公开(公告)号：US12160953B2

公开(公告)日：2024-12-03

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US20240248264A1

公开(公告)日：2024-07-25

申请号：US18623035

申请日：2024-04-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

公开(公告)号：US20240237209A9

公开(公告)日：2024-07-11

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138063A1

公开(公告)日：2024-04-25

申请号：US17986899

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Ping-Tsung Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34 ,  H05K3/40

CPC classification number: H05K1/114 ,  H05K1/024 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0195 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

公开(公告)号：US20240138059A1

公开(公告)日：2024-04-25

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K1/11 ,  H05K3/4644 ,  H05K2203/041

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US11895780B2

公开(公告)日：2024-02-06

申请号：US17194323

申请日：2021-03-08

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Wang-Hsiang Tsai ,  Cheng-Ta Ko

IPC: H05K3/46 ,  H05K3/40 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K1/14 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/36 ,  H01L23/00 ,  H01L21/683 ,  H05K1/02

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/36 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K3/4644 ,  H05K3/4673 ,  H01L23/145 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H05K1/0271 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.