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    INTEGRATED CIRCUIT LAYOUT STRUCTURE
    43.
    发明申请
    INTEGRATED CIRCUIT LAYOUT STRUCTURE 审中-公开
    集成电路布局结构

    公开(公告)号：US20160086932A1

    公开(公告)日：2016-03-24

    申请号：US14526536

    申请日：2014-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

    IPC: H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11885

    Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes at least one or more first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type.

    Abstract translation: 具有双高度标准单元的集成电路布局结构包括至少包括第一单元高度的第一标准单元和至少包括第二单元高度的第二标准单元。 第二个单元格高度是第一个单元格高度的一半。 第一标准单元包括在第一标准单元的中间形成的至少一个或多个第一掺杂区和形成在第一标准单元的顶侧和底侧的多个第二掺杂区。 第一掺杂区域包括第一导电类型，第二掺杂区域包括与第一导电类型互补的第二导电类型。

    Memory cell structure and method for forming the same
    44.
    发明授权
    Memory cell structure and method for forming the same 有权
    记忆单元结构及其形成方法

    公开(公告)号：US09136276B1

    公开(公告)日：2015-09-15

    申请号：US14255977

    申请日：2014-04-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Huang ,  Sung-Bin Lin ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Yen-Ting Ho ,  Chien-Hung Chen

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L27/11573 ,  H01L29/42348 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

    Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.

    Abstract translation: 一种用于形成存储单元结构的方法包括以下步骤。 提供至少包括限定在其上的存储单元区域的衬底，并且在存储单元区域中形成第一栅极堆叠。 执行第一LDD注入以在存储单元区域中的第一栅极堆叠的一侧形成第一LDD，并且第一LDD包括第一导电类型。 执行第二LDD注入以在存储单元区域中与第一LDD相对的第一栅极堆叠的一侧处形成第二LDD，并且第二LDD包括第一导电类型。 第一LDD和第二LDD彼此不同。

    Method for forming layout pattern of static random access memory
    45.
    发明申请
    Method for forming layout pattern of static random access memory 有权

    公开(公告)号：US20250040228A1

    公开(公告)日：2025-01-30

    申请号：US18916723

    申请日：2024-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

    IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

    Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

    Semiconductor structure and manufacturing method thereof
    46.
    发明公开
    Semiconductor structure and manufacturing method thereof 审中-公开

    公开(公告)号：US20240006405A1

    公开(公告)日：2024-01-04

    申请号：US17875430

    申请日：2022-07-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Lin ,  Chien-Hung Chen ,  Ruei-Yau Chen

    IPC: H01L27/02 ,  H01L27/118 ,  H01L21/8234

    CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L21/823481 ,  H01L2027/11831

    Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

    Integrated circuit layout structure
    49.
    发明授权
    Integrated circuit layout structure 有权

    公开(公告)号：US10290653B2

    公开(公告)日：2019-05-14

    申请号：US15466871

    申请日：2017-03-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Chun-Hsien Wu

    IPC: H01L27/118 ,  H01L27/02 ,  H01L27/092

    Abstract: An integrated circuit layout structure having dual-height standard cells includes at least a first standard cell including a first cell height and at least a second standard cell including a second cell height. The second cell height is one half of the first cell height. The first standard cell includes one first doped region formed in a middle of the first standard cell and a plurality of second doped regions formed at a top side and a bottom side of the first standard cell. The first doped region includes a first conductivity type and the second doped regions include a second conductivity type complementary to the first conductivity type. And an area of the first doped region is smaller than an area of the total second doped regions.

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