公开(公告)号：US11735644B2

公开(公告)日：2023-08-22

申请号：US17551149

申请日：2021-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/308 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20220367694A1

公开(公告)日：2022-11-17

申请号：US17330420

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Ruey-Chyr Lee

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/40

Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

公开(公告)号：US20220278222A1

公开(公告)日：2022-09-01

申请号：US17745841

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20220109058A1

公开(公告)日：2022-04-07

申请号：US17551149

申请日：2021-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/308 ,  H01L29/205 ,  H01L29/20

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US11177377B2

公开(公告)日：2021-11-16

申请号：US16726263

申请日：2019-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/34

Abstract: A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

公开(公告)号：US10971610B2

公开(公告)日：2021-04-06

申请号：US16558329

申请日：2019-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: H01L21/306 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.

公开(公告)号：US09235677B1

公开(公告)日：2016-01-12

申请号：US14333919

申请日：2014-07-17

Applicant: United Microelectronics Corp.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chen-Wei Lee ,  Chun-Liang Hou

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H01L22/12 ,  H01L22/20

Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract translation: 本发明提供一种热均匀性补偿方法和装置。 该方法的步骤包括：分别在热点效应上测量芯片的多个热点图案的多个第一电阻，其中热点图案的多个图案密度不同; 分别通过多个测试键在热点效应上测量芯片的每个热点图案的多个第二电阻，其中测试键和对应的热点图案之间的多个距离是不同的; 根据第一和第二电阻建立查找信息; 分析用于获取图案密度信息的芯片的布局数据; 以及根据图案密度信息和查找信息生成经校准的布局数据。

公开(公告)号：US09230871B1

公开(公告)日：2016-01-05

申请号：US14489460

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Kuo Wang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/088

CPC classification number: H01L22/34 ,  H01L27/088

Abstract: A test key structure includes a plurality of transistors formed on a scribe line of a wafer and arranged in a 2*N array having 2 columns and N rows. The transistors arranged in the 2*N array respectively includes a gate, a source, a drain, and a body. All of the sources of the transistors arranged in the 2*N array are electrically connected to each other.

Abstract translation: 测试键结构包括形成在晶片的划线上的多个晶体管，并且以具有2列N行的2×N阵列排列。 配置在2×N阵列中的晶体管分别包括栅极，源极，漏极和主体。 布置在2 * N阵列中的晶体管的所有源极彼此电连接。

公开(公告)号：US20140203828A1

公开(公告)日：2014-07-24

申请号：US13744498

申请日：2013-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: G01R31/26 ,  H01L23/48

CPC classification number: G01R31/2601 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract translation: 公开了包括电子矩阵，第一负载和第二负载的电子元件的布局结构。 第一负载耦合到电子矩阵的第一端，并且包括耦合到第一测试焊盘的第一测试焊盘和第二测试焊盘。 第二负载耦合到电子矩阵的第二端，并且包括耦合到第三测试垫的第三测试焊盘和第四测试焊盘。

公开(公告)号：US20250015173A1

公开(公告)日：2025-01-09

申请号：US18888136

申请日：2024-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.