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公开(公告)号:US20240088293A1
公开(公告)日:2024-03-14
申请号:US17960146
申请日:2022-10-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chun-Ya Chiu , Ssu-I Fu , Chin-Hung Chen , Jin-Yan Chiou , Wei-Chuan Tsai , Yu-Hsiang Lin
IPC: H01L29/78 , H01L21/265 , H01L21/324 , H01L29/66
CPC classification number: H01L29/7847 , H01L21/26506 , H01L21/324 , H01L29/665
Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.
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公开(公告)号:US20230170261A1
公开(公告)日:2023-06-01
申请号:US18104307
申请日:2023-02-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chun-Ya Chiu , Chi-Ting Wu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L21/8234 , H01L29/06 , H01L27/088
CPC classification number: H01L21/823481 , H01L21/823431 , H01L29/0649 , H01L27/0886
Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
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公开(公告)号:US11631613B2
公开(公告)日:2023-04-18
申请号:US17185443
申请日:2021-02-25
Applicant: United Microelectronics Corp.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chia-Jung Hsu , Chun-Ya Chiu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L27/146 , H01L21/768 , H01L27/108
Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.
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公开(公告)号:US20220093742A1
公开(公告)日:2022-03-24
申请号:US17511586
申请日:2021-10-27
Applicant: United Microelectronics Corp.
Inventor: Chia-Jung Hsu , Chin-Hung Chen , Chun-Ya Chiu , Chih-Kai Hsu , Ssu-I Fu , Tsai-Yu Wen , Shi You Liu , Yu-Hsiang Lin
IPC: H01L29/10 , H01L21/265 , H01L29/06 , H01L29/167
Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.
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公开(公告)号:US20220005957A1
公开(公告)日:2022-01-06
申请号:US17476461
申请日:2021-09-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chin-Hung Chen , Ssu-I Fu , Chih-Kai Hsu , Chun-Ya Chiu , Chia-Jung Hsu , Yu-Hsiang Lin
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/306 , H01L21/02
Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
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公开(公告)号:US20210202308A1
公开(公告)日:2021-07-01
申请号:US17185443
申请日:2021-02-25
Applicant: United Microelectronics Corp.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chia-Jung Hsu , Chun-Ya Chiu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L21/768 , H01L27/108
Abstract: Provided is a semiconductor device, including a substrate including a pixel region, a gate structure on the substrate in the pixel region, wherein the gate structure comprises a gate dielectric layer and a gate conductive layer on the gate dielectric layer; a dielectric layer located over the substrate and the gate structure; and a contact located in the dielectric layer and electrically connected to the gate conductive layer. The contact includes a doped polysilicon layer in contact with the gate conductive layer; a metal layer located on the doped polysilicon layer, wherein a part of the metal layer is embedded in the doped polysilicon layer; a barrier layer located between the metal layer and the doped polysilicon layer; and a metal silicide layer located between the barrier layer and the doped polysilicon layer.
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公开(公告)号:US20210193509A1
公开(公告)日:2021-06-24
申请号:US17190439
申请日:2021-03-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chun-Ya Chiu , Chi-Ting Wu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L21/762 , H01L21/8234 , H01L29/78 , H01L29/66
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure dividing the fin-shaped structure into a first portion and a second portion as the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion, a spacer around the top portion, a first epitaxial layer adjacent to one side of the top portion, and a second epitaxial layer adjacent to another side of the top portion.
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公开(公告)号:US10985048B2
公开(公告)日:2021-04-20
申请号:US16732367
申请日:2020-01-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chun-Ya Chiu , Chi-Ting Wu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L21/762 , H01L21/8234 , H01L29/78 , H01L29/66
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.
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公开(公告)号:US10347526B1
公开(公告)日:2019-07-09
申请号:US15951683
申请日:2018-04-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Chun-Ya Chiu , Chi-Ting Wu , Chin-Hung Chen , Yu-Hsiang Lin
IPC: H01L21/768 , H01L23/485 , H01L23/532
Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate structure, and a conductive element. The gate structure is on the substrate. The gate structure includes a gate electrode and a cap layer on the gate electrode. The conductive element is adjoined with an outer surface of the gate structure. The conductive element includes a lower conductive portion and an upper conductive portion electrically connected on the lower conductive portion and adjoined with the cap layer. The lower conductive portion and the upper conductive portion have an interface therebetween. The interface is below an upper surface of the cap layer.
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公开(公告)号:US20190172752A1
公开(公告)日:2019-06-06
申请号:US15830008
申请日:2017-12-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-I Fu , Yu-Hsiang Hung , Chun-Ya Chiu , Chin-Hung Chen , Chi-Ting Wu , Yu-Hsiang Lin
IPC: H01L21/8234 , H01L21/311 , H01L21/768 , H01L23/535 , H01L27/088 , H01L29/49
CPC classification number: H01L21/823475 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/76816 , H01L21/76843 , H01L21/76877 , H01L21/823431 , H01L21/823437 , H01L21/823456 , H01L21/823468 , H01L23/535 , H01L27/0886 , H01L29/4991 , H01L29/6653 , H01L29/66545
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.
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