公开(公告)号：US20200328126A1

公开(公告)日：2020-10-15

申请号：US16914483

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.

公开(公告)号：US20200227473A1

公开(公告)日：2020-07-16

申请号：US16279956

申请日：2019-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Hui Lee ,  I-Ming Tseng ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.

公开(公告)号：US20200185597A1

公开(公告)日：2020-06-11

申请号：US16216969

申请日：2018-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

公开(公告)号：US10672979B1

公开(公告)日：2020-06-02

申请号：US16281103

申请日：2019-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-An Shih ,  I-Ming Tseng ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yu-Ping Wang

IPC: H01L43/12 ,  G11C11/15 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer; forming a cap layer on the bottom electrode layer; and removing part of the cap layer, part of the bottom electrode layer, and part of the IMD layer to form a trench.

公开(公告)号：US20200035568A1

公开(公告)日：2020-01-30

申请号：US16589032

申请日：2019-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Ching-Ling Lin ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Wen-An Liang ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Yuan-Yu Chung ,  I-Ming Tseng

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.

公开(公告)号：US20180331177A1

公开(公告)日：2018-11-15

申请号：US16028386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.

公开(公告)号：US20180040694A1

公开(公告)日：2018-02-08

申请号：US15249462

申请日：2016-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer fills a lower portion of the trench. A second dielectric layer covers a top surface of the first dielectric layer, the concave upper sidewall and the rounded top corner of the trench

公开(公告)号：US09755048B2

公开(公告)日：2017-09-05

申请号：US14710602

申请日：2015-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/3086 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/785

Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.

公开(公告)号：US09608062B1

公开(公告)日：2017-03-28

申请号：US15250924

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Chen-Ming Huang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure including a fin structure formed on a substrate, and an isolation structure formed in the fin structure. The isolation structure includes a trench, and a first dielectric layer disposed in the trench wherein the first dielectric layer includes a body portion in the bottom, a protruding portion in the top with a top surface, and a shoulder portion connecting the body portion and the protruding portion. The protruding portion has a smaller width than the body portion. The semiconductor structure further includes a second dielectric layer covering a top corner of the trench and sandwiched between the protruding portion, the shoulder portion of the first dielectric layer and the upper sidewall of the trench.

公开(公告)号：US20170047244A1

公开(公告)日：2017-02-16

申请号：US15336811

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L21/762 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract translation: 翅片结构切割过程包括以下步骤。 在基板中形成有四个翅片结构，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。