公开(公告)号：US20180314773A1

公开(公告)日：2018-11-01

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F17/50

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

公开(公告)号：US09964587B2

公开(公告)日：2018-05-08

申请号：US15151748

申请日：2016-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Kuo Wang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: G01R31/02 ,  G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

公开(公告)号：US20160019330A1

公开(公告)日：2016-01-21

申请号：US14333919

申请日：2014-07-17

Applicant: United Microelectronics Corp.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chen-Wei Lee ,  Chun-Liang Hou

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H01L22/12 ,  H01L22/20

Abstract: The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information.

Abstract translation: 本发明提供一种热均匀性补偿方法和装置。 该方法的步骤包括：分别在热点效应上测量芯片的多个热点图案的多个第一电阻，其中热点图案的多个图案密度不同; 分别通过多个测试键在热点效应上测量芯片的每个热点图案的多个第二电阻，其中测试键和对应的热点图案之间的多个距离是不同的; 根据第一和第二电阻建立查找信息; 分析用于获取图案密度信息的芯片的布局数据; 以及根据图案密度信息和查找信息生成经校准的布局数据。

公开(公告)号：US20150112623A1

公开(公告)日：2015-04-23

申请号：US14059450

申请日：2013-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Kuo Wang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/14

Abstract: A method of the measuring a critical dimension of a spacer is provided. The measurement is performed by using several test structures of measuring doping region resistance. Each of the test structure has different space disposed between a first gate line and a second gate line. By measuring a doping region resistance of each test structure, a plot of reciprocal of resistance versus space can be accomplished. Then, making regression of the plot, a correlation can be formed. Finally, a critical dimension of a spacer can be get by extrapolating the correlation back to 0 unit of reciprocal of resistance.

Abstract translation: 提供了一种测量间隔物临界尺寸的方法。 通过使用测量掺杂区域电阻的几个测试结构来进行测量。 每个测试结构具有设置在第一栅极线和第二栅极线之间的不同空间。 通过测量每个测试结构的掺杂区域电阻，可以实现电阻与空间的倒数的曲线。 然后，使情节回归，可以形成一个相关性。 最后，可以通过将相关性推回到0单位的电阻倒数来获得间隔物的临界尺寸。

公开(公告)号：US20140354325A1

公开(公告)日：2014-12-04

申请号：US13903102

申请日：2013-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: G01R31/26

CPC classification number: H01L22/34 ,  G01R31/2831 ,  G01R31/2858 ,  G01R31/2884

Abstract: A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage.

Abstract translation: 公开了一种半导体布局结构及其测试方法。 半导体布局结构包括被测器件（DUT），第一测试焊盘，第二测试焊盘和多个第三测试焊盘。 DUT包括多个金属氧化物半导体（MOS）晶体管。 每个MOS晶体管包括第一端子，第二端子和第三端子。 第一测试焊盘耦合到第一端子以施加第一电压。 第二测试垫耦合到第二端子以施加第二电压。 第三测试焊盘分别耦合到第三测试焊盘以施加第三电压。 第三个测试垫彼此电绝缘。 第三电压大于第一电压和第二电压。

公开(公告)号：US12113098B2

公开(公告)日：2024-10-08

申请号：US18123972

申请日：2023-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Kuang-Pi Lee ,  Wen-Jung Liao

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L27/0605 ,  H01L27/0629

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

公开(公告)号：US20240234539A9

公开(公告)日：2024-07-11

申请号：US18395657

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20240222437A1

公开(公告)日：2024-07-04

申请号：US18608890

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66431 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.

公开(公告)号：US12027604B2

公开(公告)日：2024-07-02

申请号：US18215787

申请日：2023-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US11935947B2

公开(公告)日：2024-03-19

申请号：US16596738

申请日：2019-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/49

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/7787

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.