-
公开(公告)号：US12072756B2
公开(公告)日：2024-08-27
申请号：US17854710
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas K. Sridharan , Dean A. Liberty , Magiting Talisayon , Srikanth Masanam
CPC classification number: G06F11/0772 , G06F11/0787 , G06F11/1405 , G06F12/0292
Abstract: An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.
-
公开(公告)号：US12056713B2
公开(公告)日：2024-08-06
申请号：US18149493
申请日：2023-01-03
Applicant: Capital One Services, LLC
Inventor： Nishant Srivastava , Eric K. Barnum , Suresh Chander Ramaraj , Eric Smith , Earle Michael Lee , Kumari Bhawprita
CPC classification number: G06Q20/425 , G06F11/0745 , G06F11/0757 , G06F11/1405 , G06F11/1474 , G06F16/2379 , G06Q20/085 , G06Q20/401
Abstract: Aspects described herein may relate to a transaction exchange platform using a streaming data platform (SDP) and microservices to process transactions according to review and approval workflows. The transaction exchange platform may receive transactions from origination sources, which may be added to the SDP as transaction objects. As the transactions are received, the transactions may be analyzed to detect duplicate transactions and/or errors in the transactions. The transaction exchange platform may take steps to remediate transactions that are recognized as duplicates or predicted to generate one or more errors. Similarly, the transaction exchange platform may take steps to remediate transactions that are rejected by a clearinghouse.
-
公开(公告)号：US12001284B2
公开(公告)日：2024-06-04
申请号：US16702075
申请日：2019-12-03
Applicant: salesforce.com, inc.
Inventor： Mark F. Wilding
CPC classification number: G06F11/1405 , G06F8/60 , G06F9/4881 , G06F9/541 , G06F11/1415 , G06F11/1482 , G06F11/3664 , G06F11/3692 , G06F21/51 , G06F21/54
Abstract: Techniques are disclosed relating to automated operations management. In various embodiments, a computer system accesses operational information that defines commands for an operational scenario and accesses blueprints that describe operational entities in a target computer environment related to the operational scenario. The computer system implements the operational scenario for the target computer environment. The implementing may include executing a hierarchy of controller modules that include an orchestrator controller module at top level of the hierarchy that is executable to carry out the commands by issuing instructions to controller modules at a next level. The controller modules may be executable to manage the operational entities according to the blueprints to complete the operational scenario. In various embodiments, the computer system includes additional features such as an application programming interface (API), a remote routing engine, a workflow engine, a reasoning engine, a security engine, and a testing engine.
-
公开(公告)号：US11915247B2
公开(公告)日：2024-02-27
申请号：US17888297
申请日：2022-08-15
Applicant: Stripe, Inc.
Inventor： Tara Seshan , Adam Eagle
CPC classification number: G06Q20/425 , G06F11/1405 , G06N20/00
Abstract: In an example embodiment, information about one or more failed payment attempts via an electronic payment processing system is obtained. One or more features are extracted from the information. Then, for each of a plurality of potential candidate retry time points, the one or more features and the potential candidate retry time point are fed into a dunning model, the dunning model trained via a machine-learning algorithm to produce a dunning score indicative of a likelihood that a retry attempt at an input retry time point will result in a successful payment processing. The dunning scores for the plurality of potential candidate retry time points are used to select a desired retry time point. Then the electronic payment processing system is caused to attempt to reprocess a payment associated with one of the failed payment attempts at a time matching the desired retry time point.
-
公开(公告)号：US20240045764A1
公开(公告)日：2024-02-08
申请号：US18483340
申请日：2023-10-09
Applicant: Salesforce, Inc.
Inventor： Mark F. Wilding
CPC classification number: G06F11/1405 , G06F9/4881 , G06F9/541 , G06F11/3664 , G06F21/54 , G06F11/1482 , G06F11/3692 , G06F11/1415 , G06F21/51 , G06F8/60
Abstract: Techniques are disclosed relating to automated operations management. In various embodiments, a computer system accesses operational information that defines commands for an operational scenario and accesses blueprints that describe operational entities in a target computer environment related to the operational scenario. The computer system implements the operational scenario for the target computer environment. The implementing may include executing a hierarchy of controller modules that include an orchestrator controller module at top level of the hierarchy that is executable to carry out the commands by issuing instructions to controller modules at a next level. The controller modules may be executable to manage the operational entities according to the blueprints to complete the operational scenario. In various embodiments, the computer system includes additional features such as an application programming interface (API), a remote routing engine, a workflow engine, a reasoning engine, a security engine, and a testing engine.
-
Patent Agency Ranking
46.发明公开公开(公告)号：US20230315573A1
公开(公告)日：2023-10-05
申请号：US18101875
申请日：2023-01-26
Applicant: Fujitsu Limited
Inventor： Yasuhiro Kitamura
CPC classification number: G06F11/1405 , G06F9/30079 , G06F11/0772
Abstract: A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.
-
公开(公告)号：US09910731B2
公开(公告)日：2018-03-06
申请号：US15357448
申请日：2016-11-21
Applicant: Cray Inc.
Inventor： Laurence S. Kaplan , Preston Pengra Briggs, III , Miles Arthur Ohlrich , Willard Huston Leslie
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/067 , G06F3/0673 , G06F11/08 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1016 , G06F11/1068 , G06F11/1088 , G06F11/14 , G06F11/1402 , G06F11/1405 , G06F11/141 , G06F11/1479 , G06F11/1662 , G06F11/202 , G06F11/2023 , G06F11/2035 , G06F2201/805 , G06F2201/82
Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
-
公开(公告)号：US09734023B2
公开(公告)日：2017-08-15
申请号：US14801825
申请日：2015-07-17
Applicant: Renesas Electronics Corporation
Inventor： Osamu Nishii , Kiwamu Takada
CPC classification number: G06F11/1637 , G06F11/1004 , G06F11/1405 , G06F11/1645 , G06F11/165 , G06F11/1695
Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.
-
公开(公告)号：US20170068596A1
公开(公告)日：2017-03-09
申请号：US15357448
申请日：2016-11-21
Applicant: Cray Inc.
Inventor： Laurence S. Kaplan , Preston Pengra Briggs, III , Miles Arthur Ohlrich , Willard Huston Leslie
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/067 , G06F3/0673 , G06F11/08 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1016 , G06F11/1068 , G06F11/1088 , G06F11/14 , G06F11/1402 , G06F11/1405 , G06F11/141 , G06F11/1479 , G06F11/1662 , G06F11/202 , G06F11/2023 , G06F11/2035 , G06F2201/805 , G06F2201/82
Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
Abstract translation: 弹性系统使用先前存储的纠错信息来检测和校正由计算系统的存储器系统报告的存储器错误。 当程序将数据存储到存储器位置时，在计算系统上执行的弹性系统生成并存储纠错信息。 当程序然后执行加载指令以从存储器位置检索数据时，如果没有存储器错误，则加载指令正常完成。 然而，如果存在内存错误，则计算系统将控制权传给弹性系统（例如，经由陷阱）来处理存储器错误。 弹性系统检索存储器位置的纠错信息并重新创建存储器位置的数据。 弹性系统存储数据，就好像加载指令已经正常完成，并将控制权传给程序的下一条指令。
-
公开(公告)号：US20170046140A1
公开(公告)日：2017-02-16
申请号：US15335709
申请日：2016-10-27
Applicant: Intel Corporation
Inventor： Abhay S. Kanhere , Saurabh Shukla , Suriya Subramanian , Paul Caprioli
CPC classification number: G06F8/443 , G06F9/45516 , G06F11/1405 , G06F2201/805
Abstract: State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting, with a processor, a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code, maintaining, with the processor, a first indication of a first manner in which the first portion of the register is to be restored in connection with a state recovery after execution of the region of the optimized code, and maintaining, with the processor, a second indication of a second manner in which a second portion of the register is to be restored in connection with the state recovery after execution of the region of the optimized code.
Abstract translation: 披露了用于计算平台的状态恢复方法和装置。 一个示例性方法包括：利用处理器将第一指令插入到优化的代码中，以使得在执行优化代码的区域之前将处于第一状态的寄存器的第一部分保存到存储器， 与执行优化代码的区域之后的状态恢复相关联地恢复寄存器的第一部分的第一方式的第一指示，并且用处理器维持第二方式的第二指示，其中第二指示 寄存器的第二部分将在执行优化代码的区域之后与状态恢复相关联地恢复。
-
-
-
-
-
-
-
-
-
Search Results
212
records
(took 0.021 seconds)
