公开(公告)号：US11860732B2

公开(公告)日：2024-01-02

申请号：US17459846

申请日：2021-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Juane Li ,  Fangfang Zhu ,  Seungjune Jeon ,  Yueh-Hung Chen

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/3037 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.

公开(公告)号：US20230418607A1

公开(公告)日：2023-12-28

申请号：US18144569

申请日：2023-05-08

Applicant: Lodestar Licensing Group, LLC

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F9/30 ,  G06F9/48 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F9/30047 ,  G06F9/4806 ,  G06F3/0659 ,  G06F3/0646 ,  G06F3/0679 ,  G06F3/0617 ,  G06F3/0613 ,  G06F12/1009 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US11854603B2

公开(公告)日：2023-12-26

申请号：US17540682

申请日：2021-12-02

Applicant: Western Digital Technologies, Inc.

Inventor： Atif Hussain ,  Vivek Shivhare

IPC: G11C16/04 ,  G11C11/408 ,  G06F12/02 ,  H03K19/17728

CPC classification number: G11C11/4087 ,  G06F12/0246 ,  G11C11/4085 ,  H03K19/17728 ,  G06F2212/7201

Abstract: A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory.

公开(公告)号：US11853230B2

公开(公告)日：2023-12-26

申请号：US17329989

申请日：2021-05-25

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0238 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US11853200B2

公开(公告)日：2023-12-26

申请号：US17653323

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/0292 ,  G06F12/0891 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.

公开(公告)号：US20230409470A1

公开(公告)日：2023-12-21

申请号：US17841378

申请日：2022-06-15

Applicant: Western Digital Technologies, Inc.

Inventor： Ramanathan MUTHIAH

IPC: G06F12/02 ,  G06F12/0871 ,  G06F13/16

CPC classification number: G06F12/0238 ,  G06F12/0871 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Aspects of a data storage device are provided that optimize utilization of a scratchpad memory. The data storage device includes an NVM and a controller which allocates a memory location of the NVM as scratchpad memory for a host. The controller receives a command including data from a submission queue associated with the scratchpad memory, stores the data in the scratchpad memory, and disables first updates to the L2P mapping table for the data in the scratchpad memory across power cycles. The controller also receives commands from other submission queues for other memory locations than the scratchpad memory, stores data in the other memory locations, and stores second updates to a L2P mapping table. The first and second updates may include different data lengths. Thus, the device accounts for differences between scratchpad memory and NVM in at least data alignment, L2P granularity, and response, resulting in efficient scratchpad memory management.

公开(公告)号：US11841795B2

公开(公告)日：2023-12-12

申请号：US17587088

申请日：2022-01-28

Applicant: SK hynix Inc.

Inventor： Min Jun Jang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A storage device includes: a memory device including a plurality of memory blocks; a buffer memory device including first and second buffers which temporarily store write data; and a memory controller for controlling the memory device and the buffer memory device to perform a write operation of storing the write data in the memory device. The memory controller allocates a command to a mapping table including mapping information corresponding to a physical address according to a reception order of the command, when the memory controller receives the command from a host, and controls the buffer memory device such that write data is temporarily stored in a corresponding one of the first and second buffers. When write data temporarily stored in the first or second buffer is flushed to the memory device, the memory controller updates the mapping table, using mapping information corresponding to the flushed write data.

公开(公告)号：US11836117B2

公开(公告)日：2023-12-05

申请号：US17341613

申请日：2021-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hyeong Yoon ,  Won Woo Ro ,  Won Seb Jeong

IPC: G06F7/00 ,  G06F16/18 ,  G06F16/14 ,  G06F12/02

CPC classification number: G06F16/1815 ,  G06F12/0238 ,  G06F16/144 ,  G06F16/156 ,  G06F2212/7201

Abstract: A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.

公开(公告)号：US11816027B2

公开(公告)日：2023-11-14

申请号：US17561180

申请日：2021-12-23

Applicant: Western Digital Technologies, Inc.

Inventor： Ajith Kumar Battaje ,  Tanay Goel ,  Rajendra Prasad Mishra

IPC: G06F12/02 ,  G06F12/1009 ,  G06F12/0862

CPC classification number: G06F12/0246 ,  G06F12/0862 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/602 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.

公开(公告)号：US20230359552A1

公开(公告)日：2023-11-09

申请号：US17633525

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Jonathan S. Parry ,  Deping He ,  Xu Zhang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.