公开(公告)号：US20140091955A1

公开(公告)日：2014-04-03

申请号：US13976329

申请日：2012-04-19

Applicant: Nicholas P. Cowley ,  Isaac Ali

Inventor： Nicholas P. Cowley ,  Isaac Ali

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215

Abstract: According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample.

Abstract translation: 根据各种实施例，提出了一种涉及确定和校正模数（AD）转换器阵列（可被实现为宽带ADC的一部分）的输出采样之间的信号不平衡的系统，装置和方法， 。 统计模块和校正模块与A-D转换器阵列相关联。 统计模块被配置为从多个A-D转换器接收数字样本，并且使用从其接收的一组数字样本为每个A-D转换器生成统计采样值。 校正模块被配置为，对于多个AD转换器中的至少一个，通过将多个AD转换器中的至少一个AD转换器的统计采样值与参考值进行比较来确定偏移值，并将偏移值应用于 来自该至少一个AD转换器的数字样本以产生经校正的数字样本。

公开(公告)号：US08410961B2

公开(公告)日：2013-04-02

申请号：US13188459

申请日：2011-07-21

Applicant: Masaru Iwabuchi

Inventor： Masaru Iwabuchi

IPC: H03M1/00

CPC classification number: H03M1/08 ,  H03M1/46

Abstract: In combining an analog terminal of an A/D converter with a digital terminal, the effect of the noise from the digital terminal is reduced. A semiconductor integrated circuit includes a high-speed external terminal, a low-speed external terminal, a high-speed analog switch, a low-speed analog switch, and an A/D converter. The high-speed external terminal is coupled to an input of the A/D converter via the high-speed analog switch, and the low-speed external terminal is coupled to the input of the A/D converter via the low-speed analog switch. A plurality of inputs of a plurality of low-speed digital input buffer circuits and a plurality of outputs of a plurality of low-speed digital output buffer circuits are coupled to a plurality of low-speed external terminals. The output of any digital output buffer circuit is not coupled to a plurality of high-speed external terminals, but a plurality of inputs of a plurality of high-speed digital input buffer circuits is coupled to a plurality of high-speed external terminals. Between a plurality of low-speed external terminals and the input of the A/D converter, a low-speed separating resistor with a high resistance value is coupled, respectively.

Abstract translation: 在将A / D转换器的模拟端与数字端组合在一起的同时，减少了数字终端的噪声的影响。 半导体集成电路包括高速外部端子，低速外部端子，高速模拟开关，低速模拟开关和A / D转换器。 高速外部端子通过高速模拟开关耦合到A / D转换器的输入，低速外部端子通过低速模拟开关耦合到A / D转换器的输入端 。 多个低速数字输入缓冲电路的多个输入和多个低速数字输出缓冲电路的多个输出耦合到多个低速外部端子。 任何数字输出缓冲电路的输出都不耦合到多个高速外部端子，而是将多个高速数字输入缓冲电路的多个输入耦合到多个高速外部端子。 在多个低速外部端子和A / D转换器的输入端之间，分别耦合具有高电阻值的低速分离电阻器。

公开(公告)号：US20130070136A1

公开(公告)日：2013-03-21

申请号：US13570580

申请日：2012-08-09

Applicant: Hiroki Hiyama ,  Kohichi Nakamura ,  Kazuhiro Saito ,  Tetsuya Itano

Inventor： Hiroki Hiyama ,  Kohichi Nakamura ,  Kazuhiro Saito ,  Tetsuya Itano

IPC: H03M1/12 ,  H04N5/335

CPC classification number: H03M1/1245 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/1225 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/56 ,  H04N5/3577 ,  H04N5/3765 ,  H04N5/378

Abstract: In an A/D converter, a first analog signal which is input to an input terminal in a state in which the input terminal and a reference voltage line are connected via a first capacitor is converted into digital data when a reference signal is supplied to the reference signal line in a state in which the reference signal line and a first input terminal of a comparator are connected via the first capacitor. A second analog signal which is input to the input terminal in a state in which the input terminal and the reference voltage line are connected via a second capacitor is converted into digital data when the reference signal is supplied to the reference signal line in a state in which the reference signal line and the first input terminal of the comparator are connected via the second capacitor.

Abstract translation: 在A / D转换器中，当将输入端和参考电压线经由第一电容器连接的状态下输入到输入端的第一模拟信号，当将参考信号提供给 在参考信号线和比较器的第一输入端经由第一电容器连接的状态下的基准信号线。 在将输入端子和参考电压线通过第二电容器连接的状态下输入到输入端子的第二模拟信号在基准信号以基准信号线提供给基准信号线时被转换为数字数据 比较器的参考信号线和第一输入端经由第二电容器连接。

公开(公告)号：US08054210B2

公开(公告)日：2011-11-08

申请号：US12015898

申请日：2008-01-17

Applicant: Matthew Purcell ,  Rachel Elliott ,  Graeme Storm

Inventor： Matthew Purcell ,  Rachel Elliott ,  Graeme Storm

IPC: H03M1/56

CPC classification number: H03M1/08 ,  H03M1/12 ,  H03M1/34 ,  H04N5/3575 ,  H04N5/378

Abstract: An image sensor includes a pixel array, and a correlated double sample circuit coupled to one of the pixels in the pixel array. The correlated double sample circuit includes first and second inputs, and first and second sample capacitors respectively coupled to the first and second inputs. The first input is for receiving an analog signal from a pixel, and the second input is for receiving a time varying reference signal. The analog signal varies during a pixel readout period, and has a first level during a first reset period and a second-level during a second read period. A comparator circuit compares the time varying reference signal and the analog signal. The analog signal and the time varying reference signal are constantly read onto one of the first and second sample capacitors during both the first reset period and the second read period.

Abstract translation: 图像传感器包括像素阵列和耦合到像素阵列中的像素之一的相关双倍采样电路。 相关双采样电路包括第一和第二输入以及分别耦合到第一和第二输入的第一和第二采样电容器。 第一输入用于从像素接收模拟信号，第二输入用于接收时变参考信号。 模拟信号在像素读出周期期间变化，并且在第一复位周期期间具有第一电平，在第二读取周期期间具有第二电平。 比较器电路将时变参考信号与模拟信号进行比较。 在第一复位周期和第二读取周期期间，模拟信号和时变参考信号一直被读取到第一和第二采样电容器中的一个上。

公开(公告)号：US20110084862A1

公开(公告)日：2011-04-14

申请号：US12900074

申请日：2010-10-07

Applicant: Takuji Aso

Inventor： Takuji Aso

IPC: H03M1/00 ,  H03M1/34

CPC classification number: H03M1/08 ,  H03M1/46

Abstract: A high-precision A/D conversion is realized while the number of external terminals used for an A/D converter is reduced. At the time of sampling, first to fifth switches are turned on and a sixth switch is turned off. Since a first resistor is set to a resistance value optimum for sampling, an impedance in the direction from a node A to the left side and an impedance in the direction from a node B to the left side almost match, and a large noise-cancelling effect is obtained. At the time of successive approximation, the first, second, third, and fifth switches are turned off and the fourth and sixth switches are turned on. Since a second resistor is set to a resistance value optimum for the successive approximation, the impedance in the direction from the node A to the left side and the impedance in the direction from the node B to the left side almost match, and a large noise-cancelling effect is obtained also at the time of successive approximation.

Abstract translation: 实现了A / D转换器的高精度A / D转换，同时减少了A / D转换器的外部端子数量。 在采样时，第一至第五开关导通，第六开关断开。 由于将第一电阻器设置为对采样最佳的电阻值，所以从节点A向左侧的方向上的阻抗以及从节点B到左侧的阻抗几乎匹配，并且大的噪声消除 效果得到。 在逐次逼近时，第一，第二，第三和第五开关断开，第四和第六开关导通。 由于第二电阻器被设置为对于逐次逼近最佳的电阻值，所以从节点A到左侧的阻抗以及从节点B到左侧的阻抗几乎匹配，并且噪声大 在逐次逼近时也获得了取景效果。

公开(公告)号：US20110063152A1

公开(公告)日：2011-03-17

申请号：US12879892

申请日：2010-09-10

Applicant: Liang-wei Huang ,  Ting-Fa Yu ,  Ta-Chin Tseng ,  Li-Wei Fang

Inventor： Liang-wei Huang ,  Ting-Fa Yu ,  Ta-Chin Tseng ,  Li-Wei Fang

IPC: H03M1/00

CPC classification number: H03M1/08 ,  H03M1/12

Abstract: A communication device and the method thereof are disclosed in embodiments of the present invention. The communication device includes a level determining module, an digital to analog converter and an analog to digital converter. The level determining module determines a plurality of voltage levels and voltage intensity thereof according to an estimating signal to generate a first digital signal. The digital to analog converter converts the first digital signal into a pulse shaped analog signal according to the plurality of voltage levels and voltage intensity thereof. The analog to digital converter converts a first difference signal into a second digital signal wherein the first difference signal equals the result of subtracting the pulse shaped analog signal from a receiving signal.

Abstract translation: 通信装置及其方法在本发明的实施例中公开。 通信设备包括电平确定模块，数模转换器和模数转换器。 电平确定模块根据估计信号确定多个电压电平和电压强度，以产生第一数字信号。 数模转换器根据多个电压电平和电压强度将第一数字信号转换为脉冲形模拟信号。 模数转换器将第一差分信号转换成第二数字信号，其中第一差分信号等于从接收信号中减去脉冲形模拟信号的结果。

公开(公告)号：US07714267B2

公开(公告)日：2010-05-11

申请号：US11981833

申请日：2007-10-30

Applicant: W. Daniel Hillis ,  Nathan P. Myhrvold ,  Lowell L. Wood, Jr.

Inventor： W. Daniel Hillis ,  Nathan P. Myhrvold ,  Lowell L. Wood, Jr.

IPC: H01J40/14

CPC classification number: H03M1/08 ,  G01J1/18 ,  G01J1/4228 ,  H03M1/44 ,  H04N5/335

Abstract: A system is described that may determine an intensity measure. In certain example embodiments, a system may include circuitry for receiving and circuitry for assessing. The circuitry for receiving may receive an input signal at an input of a first gain element of a cascade of N gain elements. The circuitry for assessing may assess an intensity in response to one or more times associated with one or more output signals of the cascade of N gain elements satisfying one or more threshold values.

Abstract translation: 描述可以确定强度测量的系统。 在某些示例性实施例中，系统可以包括用于接收的电路和用于评估的电路。 用于接收的电路可以在N个增益元件级联的第一增益元件的输入处接收输入信号。 用于评估的电路可以响应于与满足一个或多个阈值的N个增益元件的级联的一个或多个输出信号相关联的一个或多个时间来评估强度。

公开(公告)号：US20100026546A1

公开(公告)日：2010-02-04

申请号：US12511250

申请日：2009-07-29

Applicant: Frank Ohnhaeuser ,  Andreas Wickmann

Inventor： Frank Ohnhaeuser ,  Andreas Wickmann

IPC: H03M1/12

CPC classification number: H03M1/08 ,  H03M1/0682 ,  H03M1/124 ,  H03M1/468 ,  H03M1/804

Abstract: An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.

Abstract translation: 提供了一种使用逐次逼近的模数转换电子装置。 该器件包括第一ADC级。 第一ADC级包括适于对输入电压进行采样的第一多个电容器，并且适于耦合到第一参考信号电平或第二参考信号电平。 第一多个电容器中的至少一个电容器被适配为悬空。 响应于由第二ADC级进行的模数转换决定，控制级适于将至少一个浮动电容器切换到第一参考信号电平或第二参考信号电平。

公开(公告)号：US20090146717A1

公开(公告)日：2009-06-11

申请号：US12330270

申请日：2008-12-08

Applicant: Edward Kohler ,  Michael P. Anthony

Inventor： Edward Kohler ,  Michael P. Anthony

IPC: H03H11/26

CPC classification number: H03M1/08

Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Abstract translation: 一种用于增加电荷存储装置的电荷存储容量而不改变其固有电荷转移功能的技术。 该技术可以用于实现在数字射频信号接收机中使用的诸如模数转换器（ADC）的电荷域信号处理电路。

公开(公告)号：US07471230B2

公开(公告)日：2008-12-30

申请号：US11937860

申请日：2007-11-09

Applicant: Takayuki Tooyama ,  Atsushi Suzuki ,  Noriyuki Fukushima ,  Yukihiro Yasui ,  Yoshikazu Nitta

Inventor： Takayuki Tooyama ,  Atsushi Suzuki ,  Noriyuki Fukushima ,  Yukihiro Yasui ,  Yoshikazu Nitta

IPC: H03M1/34

CPC classification number: H03M1/08 ,  H03M1/0607 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/378

Abstract: An analog to digital converter comprising a reference signal generator, a comparator, and a counter wherein the reference signal generator is operable to generate a reference for converting an analog signal into a digital signal. The reference signal generator is also operable to generate a plurality of the reference signals based on the change in a voltage. The comparator is operable to compare the analog signal with the reference signal generated by the reference signal generator. The counter is operable to count, in parallel with a comparison performed by the comparator, a predetermined count clock and to hold a count value at the time of completion of the comparison.

Abstract translation: 一种模数转换器，包括参考信号发生器，比较器和计数器，其中参考信号发生器可操作以产生用于将模拟信号转换为数字信号的参考。 参考信号发生器还可操作以基于电压的变化产生多个参考信号。 比较器可操作以将模拟信号与由参考信号发生器产生的参考信号进行比较。 计数器可操作地与比较器执行的比较并行地计数预定计数时钟，并且在比较完成时保持计数值。