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    Memory module and method having improved signal routing topology
    43.
    发明授权
    Memory module and method having improved signal routing topology 有权

    公开(公告)号：US07242213B2

    公开(公告)日：2007-07-10

    申请号：US10932477

    申请日：2004-09-01

    Applicant: George E. Pax ,  Roy E. Greeff

    Inventor： George E. Pax ,  Roy E. Greeff

    IPC: H03K19/03 ,  H01L21/8242 ,  H01L25/00 ,  G11C7/08

    CPC classification number: G11C5/04 ,  G11C5/025 ,  G11C5/063 ,  G11C11/409 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

    Multilayer board switch matrix
    44.
    发明申请
    Multilayer board switch matrix 失效
    多层板开关矩阵

    公开(公告)号：US20060139119A1

    公开(公告)日：2006-06-29

    申请号：US11020341

    申请日：2004-12-23

    Applicant: Jay Alexander ,  Anthony Cappello ,  Raymond Kaarsberg ,  Robert Patukonis

    Inventor： Jay Alexander ,  Anthony Cappello ,  Raymond Kaarsberg ,  Robert Patukonis

    IPC: H01P1/10

    CPC classification number: H05K1/0237 ,  H01P1/10 ,  H05K1/0298 ,  H05K1/117 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09727

    Abstract: A multi-layer cross connect having high isolation between signal channels, the multi-layer cross connect comprising: (a) a multi-layer circuit board having a top and bottom orientation and comprising at least a bottom layer and one or more upper layers; (b) a plurality of microstrip launches along the perimeter of the bottom layer; (c) a plurality of striplines on the bottom layer, each stripline being connected to one and only one microstrip launch and comprising a transformer for lowering its impedance and thereby increasing its width, the striplines comprising first striplines and second striplines; (d) a plurality of transition vias, each transition via conductively coupling each of the second striplines to a stripline on an upper layer; and (e) a combiner on each layer for combining signals from multiple striplines to a common stripline.

    Abstract translation: 一种在信号通道之间具有高隔离度的多层交叉连接器，所述多层交叉连接器包括：（a）多层电路板，其具有顶部和底部取向并且至少包括底层和一个或多个上层; （b）沿底层周边的多个微带发射; （c）底层上的多条带状线，每个带状线连接到一个且仅一个微带发射，并且包括用于降低其阻抗并因此增加其宽度的变压器，带状线包括第一带状线和第二带状线; （d）多个过渡通孔，每个过渡通过将每个第二带状线导电地耦合到上层上的带状线; 和（e）每个层上的组合器，用于将来自多个带状线的信号组合成公共带状线。

    Power amplifier and radio communication device using the amplifier
    46.
    发明申请
    Power amplifier and radio communication device using the amplifier 失效
    功率放大器和使用放大器的无线电通信设备

    公开(公告)号：US20060038612A1

    公开(公告)日：2006-02-23

    申请号：US11258170

    申请日：2005-10-26

    Applicant: Yuta Araki ,  Hiroyuki Kayano ,  Keiichi Yamaguchi

    Inventor： Yuta Araki ,  Hiroyuki Kayano ,  Keiichi Yamaguchi

    IPC: H03F3/68

    CPC classification number: H03F1/0277 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/429 ,  H05K1/0265 ,  H05K1/165 ,  H05K2201/09254 ,  H05K2201/09263

    Abstract: A power amplifier includes amplifier elements to amplify input signals of different frequencies. The amplifier also includes a power supply circuit that includes a common power supply path including an end connected to a power supply input terminal connected to a DC power supply. The amplifier further includes individual power supply paths each including an end connected to the other end of the common power supply path, and the other end connected to the main electrode of a corresponding one of the amplifier elements. The individual power supply paths have different impedances.

    Abstract translation: 功率放大器包括用于放大不同频率的输入信号的放大器元件。 放大器还包括电源电路，其包括公共电源路径，其包括连接到连接到DC电源的电源输入端的端部。 放大器还包括单独的电源路径，每个电源路径包括连接到公共电源路径的另一端的端部，另一端连接到相应的一个放大器元件的主电极。 各个电源路径具有不同的阻抗。

    Memory module with improved data bus performance
    49.
    发明授权
    Memory module with improved data bus performance 有权
    内存模块具有改进的数据总线性能

    公开(公告)号：US06990543B2

    公开(公告)日：2006-01-24

    申请号：US10883488

    申请日：2004-07-01

    Applicant: Myun-joo Park ,  Byung-se So

    Inventor： Myun-joo Park ,  Byung-se So

    IPC: G11C8/00

    CPC classification number: H05K1/0216 ,  G06F13/1684 ,  G11C5/04 ,  G11C5/06 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2203/1572

    Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

    Abstract translation: 存储器模块能够构成可以减少整个通道的长度的短循环形式的存储器总线系统。 结果，该系统适用于高速操作，并且可以减少制造诸如板和模块连接器的系统的成本。 存储器模块包括位于存储器模块的前部和后侧的一侧中的多个突片，用于通过系统板上的连接器互连，用于连接两个不同信号层的多个通孔 存储器模块和多个数据总线通过每个通孔从存储器模块的前面的突出部延伸到存储器模块的后部上的突出部。 至少一个存储器件连接到每个数据总线。 优选地，每个数据总线形成为垂直于其上形成有突片的存储器模块的一侧。

    DDR memory modules with input buffers driving split traces with trace-impedance matching at trace junctions
    50.
    发明授权
    DDR memory modules with input buffers driving split traces with trace-impedance matching at trace junctions 失效
    具有输入缓冲器的DDR存储器模块驱动具有跟踪结点的跟踪阻抗匹配的分段迹线

    公开(公告)号：US06947304B1

    公开(公告)日：2005-09-20

    申请号：US10249845

    申请日：2003-05-12

    Applicant: Yao Tung Yen

    Inventor： Yao Tung Yen

    IPC: G11C5/06 ,  G11C7/10 ,  H05K1/02

    CPC classification number: H05K1/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1072 ,  H05K1/0245 ,  H05K2201/09254 ,  H05K2201/09727

    Abstract: A memory module has improved signal propagation delays for signals externally driven such as from a motherboard. Reflections from junctions of wiring traces on the memory module are reduced or eliminated. An input buffer or register receives a signal from the motherboard and splits the signal to drive two outputs to two separate traces. Each trace is enlarged in width or thickness, such as by using a double-width wiring trace. At the fare end of each double-width trace, a junction is made to two minimum-width traces that connect to small stub traces to DRAM inputs. Reflections from the junction are eliminated or reduced by trace-impedance matching, since the input impedance of the double-width trace from the input buffer is about the same as the combined impedance of the two minimum-width traces. Trace-input matching and input buffering can improve signal integrity and overall propagation delay.

    Abstract translation: 存储器模块具有改善的外部驱动信号（例如从主板）的信号传播延迟。 减少或消除了存储器模块上布线迹的接点的反射。 输入缓冲器或寄存器从主板接收信号并分离信号以将两个输出驱动到两个独立的迹线。 每个迹线的宽度或厚度都会扩大，例如使用双宽度布线。 在每个双宽度迹线的端点处，连接到两条最小宽度的迹线，将其连接到DRAM输入的小短截线。 由于来自输入缓冲器的双宽度迹线的输入阻抗与两个最小宽度迹线的组合阻抗大致相同，所以通过迹线阻抗匹配消除或减少了结的反射。 跟踪输入匹配和输入缓冲可以提高信号完整性和整体传播延迟。

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