公开(公告)号：US06624500B2

公开(公告)日：2003-09-23

申请号：US09998924

申请日：2001-11-29

Applicant: Junya Takafuji

Inventor： Junya Takafuji

IPC: H01L2900

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09763 ,  H01L2924/00

Abstract: An object of the invention is to provide a thin-film electronic component and a motherboard in which coupling strength of an external terminal to a supporting substrate is improved. The thin-film electronic component comprising: a supporting substrate; a lower electrode formed on part of the supporting substrate; an insulation layer formed on the lower electrode; an upper electrode formed on the insulation layer; a connection electrode which is formed on part of the supporting substrate located on a bottom surface of a through hole formed on the insulation layer, and is electrically connected to the lower electrode; and an external terminal disposed on the connection electrode within the through hole.

公开(公告)号：US20030168727A1

公开(公告)日：2003-09-11

申请号：US10092548

申请日：2002-03-08

Inventor： Junichi Kimura

IPC: H01L023/053

CPC classification number: H05K1/16 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09763

Abstract: A multi-layer board includes a ceramic layer and plural resin layers which are stacked together. The ceramic layer is provided with an impedance element formed thereon, and the uppermost resin layer is provided with an electronic component mounted thereon. The multi-layer board is stable against a temperature change.

Abstract translation: 多层板包括层叠在一起的陶瓷层和多个树脂层。 陶瓷层上形成有阻抗元件，最上面的树脂层设有安装在其上的电子部件。 多层板对温度变化是稳定的。

公开(公告)号：US20030162386A1

公开(公告)日：2003-08-28

申请号：US10240330

申请日：2003-03-06

Inventor： Tsuyoshi Ogawa ,  Yuji Nishitani ,  Akihiko Okubora

IPC: H01L051/40 ,  H01L021/301 ,  H01L021/46 ,  H01L021/78 ,  H01L021/4763 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H05K3/4682 ,  H01L21/4846 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1531 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/095 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/183 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4605 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/1189 ,  H01L2924/00

Abstract: A wiring circuit block (2) is produced by forming a release layer (6) on one of planarized principal surfaces of a mother substrate (1), forming an insulating layer (7) on the release layer (6), patterning the insulating layer (7) and forming a wiring layer (8) on the patterned insulating layer (7), and separating the insulating layer (7) and wiring layer (8) from the release layer (6) on the mother substrate (1). The circuit block (2) has components (12), (13) and (17) deposited on the wiring layer (8), and is mounted on a base circuit board (3) to provide a wiring device. Also, semiconductor chips (62) are mounted on the circuit block (2), and the circuit block (2) is mounted on a base circuit board (64) to provide a semiconductor device.

Abstract translation: 通过在母基板（1）的平坦化主面之一上形成剥离层（6），在剥离层（6）上形成绝缘层（7）而形成布线电路块（2），对绝缘层 （7），并且在图案化绝缘层（7）上形成布线层（8），并将绝缘层（7）和布线层（8）与母基板（1）上的剥离层（6）分离。 电路块（2）具有沉积在布线层（8）上的部件（12），（13）和（17），并且安装在基板（3）上以提供布线装置。 此外，半导体芯片（62）安装在电路块（2）上，并且电路块（2）安装在基底电路板（64）上以提供半导体器件。

公开(公告)号：US06606793B1

公开(公告)日：2003-08-19

申请号：US09628486

申请日：2000-07-31

Applicant: Gregory J. Dunn

Inventor： Gregory J. Dunn

IPC: H01K310

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/49156 ,  Y10T29/49167

Abstract: A method for forming an embedded low profile capacitor in a multilayer printed circuit board. The method entails providing a first metal plate on a dielectric substrate. A dielectric layer of a photopolymeric material is applied onto a first region of the first metal plate, surrounded by a second region that is exposed. A second metal plate is deposited onto the dielectric layer and the second region of the first metal plate. The second plate is then patterned to decline an upper electrode on the dielectric layer that is electrically isolated from the first metal plate. This may be accomplished by forming a trench in the second metal plate above the dielectric layer. In one aspect, the resulting capacitor thus comprises a lower electrode structure derived mainly from the first metal plate, a dielectric layer overlying the first region of the first metal plate and an upper electrode overlying the dielectric layer. The lower metal structure also includes an extension deposited onto the second region of the first metal layer about the dielectric layer and including a lip overlying a perimeter of the dielectric layer surface.

Abstract translation: 一种在多层印刷电路板中形成嵌入式薄型电容器的方法。 该方法需要在电介质基底上提供第一金属板。 将光聚合材料的电介质层施加到第一金属板的第一区域上，被暴露的第二区域包围。 第二金属板沉积在第一金属板的电介质层和第二区上。 然后对第二板进行图案化以使与第一金属板电隔离的电介质层上的上电极下降。 这可以通过在介电层上方的第二金属板中形成沟槽来实现。 一方面，所得到的电容器包括主要由第一金属板衍生的下电极结构，覆盖第一金属板的第一区域的电介质层和覆盖在电介质层上的上电极。 下部金属结构还包括在电介质层周围沉积到第一金属层的第二区域上的延伸部分，并且包括覆盖在电介质层表面的周边上的唇缘。

公开(公告)号：US20030086248A1

公开(公告)日：2003-05-08

申请号：US10281712

申请日：2002-10-28

Inventor： Naohiro Mashino

IPC: H05K007/06

CPC classification number: H01L23/642 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/141 ,  H05K1/162 ,  H05K3/42 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/10734

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer comprises: a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor comprises: a first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes; a dielectric layer formed on the first electrode; and a second electrode formed on the dielectric layer.

Abstract translation: 适于在安装板和要安装在安装板上的半导体芯片之间使用的插入器。 插入件包括：具有第一和第二表面的耐热绝缘体，所述绝缘体设置有在所述第一表面和所述第二表面处开口的多个通孔; 通过设置在至少一个通孔的内壁上的导体彼此电连接的绝缘体的第一和第二表面上形成的布线图案; 和电容器。 电容器包括：第一电极，形成在绝缘体上，并具有形成在至少一个其它通孔的内壁上的连接部分; 形成在所述第一电极上的电介质层; 以及形成在电介质层上的第二电极。

公开(公告)号：US06552384B2

公开(公告)日：2003-04-22

申请号：US09898670

申请日：2001-07-02

Applicant: Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

Inventor： Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

IPC: H01L2362

CPC classification number: H01L28/40 ,  H01L2224/4813 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

公开(公告)号：US06498714B1

公开(公告)日：2002-12-24

申请号：US09679328

申请日：2000-10-04

Applicant: Akira Fujisawa ,  Akihito Takano ,  Masayuki Sasaki

Inventor： Akira Fujisawa ,  Akihito Takano ,  Masayuki Sasaki

IPC: H01G4228

CPC classification number: H01G9/15 ,  H05K1/162 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315

Abstract: The present invention relates to a thin film capacitor device having a copper wiring layer, a dielectric layer, and a barrier layer interposed between the wiring layer and the dielectric layer. The barrier layer has the function of preventing diffusion of copper of the wiring layer. The thin film capacitor device may also include an insulating substrate, a planarizing layer, an adhesion layer, and an intermediate layer. The present invention may also relate to a printed circuit substrate having the described thin film capacitor device built therein as a capacitor.

Abstract translation: 本发明涉及一种具有铜布线层，电介质层和插入在布线层和电介质层之间的阻挡层的薄膜电容器器件。 阻挡层具有防止配线层的铜扩散的功能。 薄膜电容器器件还可以包括绝缘衬底，平坦化层，粘合层和中间层。 本发明还可以涉及一种其中内置有作为电容器的所述薄膜电容器装置的印刷电路基板。

公开(公告)号：US20020182374A1

公开(公告)日：2002-12-05

申请号：US10104975

申请日：2002-03-22

Inventor： I-Chung Tung

IPC: B32B001/06

CPC classification number: H05K1/167 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T156/103 ,  Y10T428/24694

Abstract: A method for fabricating an organic circuit board having embedded passive components, such as resistors, capacitors and inductors, is disclosed. In embedding a resistor or capacitor, a passive unit of a resistive film or a capacitive film is first made on one side of a conductive foil. In forming an inductor, a soft magnetic film is first made on one side of a conductive foil. The foil with the soft magnetic film is then introduced into the multilayer circuit board processing. The electrodes for various passive components or spiral coils for the inductive components and electrical circuit pattern are finally made on the same conductive foil simultaneously. The soft magnetic film deposited on the top of the spiral coil may be made to further improve inductor performance.

Abstract translation: 公开了一种用于制造具有诸如电阻器，电容器和电感器的嵌入式无源元件的有机电路板的方法。 在嵌入电阻器或电容器时，首先在导电箔的一侧制造电阻膜或电容膜的无源单元。 在形成电感器时，首先在导电箔的一侧制造软磁性膜。 然后将具有软磁膜的箔引入到多层电路板处理中。 用于感应部件和电路图案的各种无源部件或螺旋线圈的电极最终同时在相同的导电箔上制成。 沉积在螺旋线圈顶部的软磁膜可以进一步提高电感器性能。

公开(公告)号：US20020171530A1

公开(公告)日：2002-11-21

申请号：US10113621

申请日：2002-03-28

Applicant: VICTOR COMPANY OF JAPAN, LIMITED

Inventor： Motoshi Shindoh ,  Shigeru Michiwaki ,  Koichi Kamiyama ,  Hisanori Yoshimizu

IPC: H01F005/00

CPC classification number: H05K1/162 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361

Abstract: The present invention provides a thin film capacitance element having minimal deviation of capacitance value in a high accuracy formed on a printed circuit board (core material). The thin film capacitance element formed on a printed circuit board is composed of a lower electrode layer formed on the printed circuit board through an insulation layer, a dielectric layer formed on the lower electrode layer, an upper electrode layer formed on the dielectric layer and an electric pad for leading out the lower electrode layer, wherein the lower electrode layer is longer than the upper electrode layer in the horizontal direction and connected to the electric pad for leading out the lower electrode layer outside, and wherein the top surface of the upper electrode layer and the top surface of the electric pad for leading out the lower electrode layer are formed substantially in the same height.

Abstract translation: 本发明提供一种在印刷电路板（芯材）上形成的高精度的电容值偏差最小的薄膜电容元件。 形成在印刷电路板上的薄膜电容元件由通过绝缘层形成在印刷电路板上的下电极层，形成在下电极层上的电介质层，形成在电介质层上的上电极层和 用于引出下电极层的电焊盘，其中下电极层在水平方向上比上电极层长，并且连接到用于将下电极层引出外部的电焊盘，并且其中上电极的顶表面 并且用于引出下电极层的电焊盘的顶表面基本上形成为相同的高度。

公开(公告)号：US20020003261A1

公开(公告)日：2002-01-10

申请号：US09898670

申请日：2001-07-02

Applicant: Alps Electric Co., Ltd.

Inventor： Shinji Murata ,  Ken Yamamura ,  Mitsuru Tokuta

IPC: H01L023/62 ,  H01L029/00 ,  H01L023/495

CPC classification number: H01L28/40 ,  H01L2224/4813 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2201/09909

Abstract: In order to provide an electronic circuit board capable of preventing the breakdown voltage of a capacitor element from dropping and excellent in high frequency performance, a positive type photoresist is spin-coated over the surface of an alumina substrate and is exposed to light and developed to form an insulating layer partially, followed by formation of a capacitor element by successively stacking a lower electrode, a dielectric layer and an upper electrode over this insulating layer, further followed by formation of a resistance element, an inductor element and a transmission line, each in a filmy state, over the surface of the alumina substrate.

Abstract translation: 为了提供能够防止电容器元件的击穿电压下降且高频性能优异的电子电路板，将正型光致抗蚀剂旋涂在氧化铝基板的表面上并暴露于光并显影至 形成绝缘层，接着通过在该绝缘层上依次层叠下电极，电介质层和上电极而形成电容器元件，然后形成电阻元件，电感器元件和传输线，每个 在薄膜状态下，在氧化铝基底的表面上。