公开(公告)号：US20180267746A1

公开(公告)日：2018-09-20

申请号：US15684975

申请日：2017-08-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takayuki ITOH ,  Atsushi MATSUMURA ,  Tomoya KODAMA

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/08

CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0658 ,  G06F11/08 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: According to an embodiment, a readout control device includes a memory and one or more processors configured to function as a converter, a reader and an analyzer. The converter converts a logical address of a compressed cluster that is a readout target into a physical address in a non-volatile memory. The reader reads out, from the non-volatile memory, data included in a packing unit at a position indicated by the physical address. The analyzer analyzes header information included in the packing unit, in parallel to reading of the data included in the packing unit, and acquires position information of the compressed cluster that is the readout target in the packing unit.

公开(公告)号：US10078550B2

公开(公告)日：2018-09-18

申请号：US14842356

申请日：2015-09-01

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takao Marukame ,  Yoshifumi Nishi ,  Yusuke Higashi ,  Jiezhi Chen ,  Kazuya Matsuzawa ,  Yuichiro Mitani

IPC: G06F11/10 ,  G06F13/00 ,  G06F11/08 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/35 ,  H03M13/00 ,  H03M13/15

CPC classification number: G06F11/1076 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/353 ,  H03M13/6516

Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

公开(公告)号：US10049001B1

公开(公告)日：2018-08-14

申请号：US14671800

申请日：2015-03-27

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Thomas A. Volpe

IPC: G06F11/10 ,  G06F9/455 ,  G06F11/08 ,  H03M13/03 ,  G06F9/46 ,  H03M13/05

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or direct attached storage device. Data written to or read from storage devices may acquire errors in transit. The I/O adapter device may implement processes to generate or check error correction values, where the error correction values are provided to verify the correctness of the written or read value. The I/O adapter device may determine the portion of the data to be used in calculating the error correction value in a flexible and configurable manner.

公开(公告)号：US09979566B2

公开(公告)日：2018-05-22

申请号：US15277577

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brent R. Rothermel ,  Todd M. Rimmer

IPC: G06F11/08 ,  G06F11/14 ,  H04L25/03 ,  H04L27/20

CPC classification number: H04L25/03006 ,  G06F11/08 ,  G06F11/14 ,  H04L1/004 ,  H04L1/0047 ,  H04L1/1829

Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

公开(公告)号：US20170322841A1

公开(公告)日：2017-11-09

申请号：US15462185

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/08 ,  H04L1/00 ,  G06F13/00 ,  G06F11/16 ,  H04L1/18

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US09772899B2

公开(公告)日：2017-09-26

申请号：US14703714

申请日：2015-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

IPC: G06F11/08 ,  G11C29/52 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02 ,  H03M13/13

CPC classification number: G06F11/08 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/13

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Once Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

公开(公告)号：US09767109B2

公开(公告)日：2017-09-19

申请号：US15215614

申请日：2016-07-21

Applicant: International Business Machines Corporation

Inventor： Jason K. Resch ,  Wesley Leggette

IPC: G06F17/00 ,  G06F17/30 ,  G06F11/08 ,  G06F11/10 ,  G06F21/60 ,  G06F3/06 ,  H04L29/08

CPC classification number: G06F17/30106 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/067 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F17/30002 ,  G06F17/30079 ,  G06F17/30091 ,  G06F17/30194 ,  G06F21/602 ,  H04L67/1097

Abstract: A method begins by a dispersed storage (DS) processing module identifying a candidate dispersed storage (DS) unit of a dispersed storage network (DSN). In response to a data migration request, the method continues with the DS processing module receiving a migration receptiveness message from the candidate DS unit. In response to a data migration reference message, the method continues with the DS processing module receiving, from another DS unit of a set of DS units, a migration reference response that includes an indication of storage utilized by the other DS unit. The method continues with the DS processing module determining a storage utilization of the candidate DS unit based on the migration reference response and when the determined storage utilization compares favorably to the reported storage utilization, enabling transfer of data from a DS unit of another set of DS units to the candidate DS unit.

公开(公告)号：US09733870B2

公开(公告)日：2017-08-15

申请号：US14705115

申请日：2015-05-06

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C7/10 ,  G06F11/08 ,  G11C29/04

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/08 ,  G06F11/1032 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1051 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

公开(公告)号：US09658920B1

公开(公告)日：2017-05-23

申请号：US13924374

申请日：2013-06-21

Applicant: Altera Corporation

Inventor： Yin Chong Hew

IPC: G06F11/08 ,  G06F11/00

CPC classification number: G06F11/1004

Abstract: A method of correcting a configuration memory frame may include identifying an erroneous memory frame in a plurality of memory frames in the integrated circuit. The erroneous memory frame may be identified with error detection circuitry on the integrated circuit. A portion of data stored in an off-chip memory module may be read with controller circuitry. The read data portion may correspond to the erroneous memory frame. The erroneous memory frame may thus be corrected by loading the read data portion into the erroneous memory frame during normal operation of the integrated circuit. Every memory bit in the erroneous memory frame may be replaced or overwritten when the read data portion is loaded into the erroneous memory frame. The integrated circuit may be partially reconfigured when the erroneous memory frame is corrected.

公开(公告)号：US09652487B1

公开(公告)日：2017-05-16

申请号：US13570030

申请日：2012-08-08

Applicant: Kestutis Patiejunas

Inventor： Kestutis Patiejunas

IPC: G06F17/30 ,  G06F11/08

CPC classification number: G06F17/30371 ,  G06F11/08

Abstract: Techniques for performing data-related operations using data storage devices are described herein. Data storage devices are configured and/or enabled to perform data operations against one or more logical data addresses thereon. The data storage device receives a request including at least executable instructions defining the data operations to be performed and a range of logical data addresses upon which to execute the data operations. Upon request, either the same request as the one defining the data operations or in a separate request, the defined data operations are executed against the specified logical data addresses.