公开(公告)号：US12205631B2

公开(公告)日：2025-01-21

申请号：US18070484

申请日：2022-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hsiu Wu ,  Tsung-Hsun Wu

IPC: G11C11/24 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.

公开(公告)号：US12201032B2

公开(公告)日：2025-01-14

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H10N50/85 ,  H10B61/00 ,  H10N50/80 ,  H10N50/01

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US20250017024A1

公开(公告)日：2025-01-09

申请号：US18231448

申请日：2023-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-An HUANG ,  Shu-Hung YU ,  Chuan-Fu WANG

IPC: H10B63/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of interconnection layers disposed along a first direction, a memory element in the plurality of interconnection layers, a first conductive structure in the plurality of interconnection layers and electrically connected to the memory element, and a second conductive structure in the plurality of interconnection layers and electrically connected to the memory element. The first conductive structure includes a first conductive line and a second conductive line disposed along the first direction. The second conductive structure includes a third conductive line and a fourth conductive line disposed along the first direction. The second conductive line and the memory element are in the same interconnection layer. The third conductive line and the fourth conductive line are above the first conductive line and the second conductive line.

公开(公告)号：US20250015165A1

公开(公告)日：2025-01-09

申请号：US18888169

申请日：2024-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/66 ,  H01L21/762

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

公开(公告)号：US20250015142A1

公开(公告)日：2025-01-09

申请号：US18892494

申请日：2024-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

公开(公告)号：US20250014941A1

公开(公告)日：2025-01-09

申请号：US18227991

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yuan Wen ,  Lung-En Kuo ,  Chung-Yi Chiu

IPC: H01L21/762

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

公开(公告)号：US12193342B2

公开(公告)日：2025-01-07

申请号：US18239108

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

公开(公告)号：US20250008745A1

公开(公告)日：2025-01-02

申请号：US18221872

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20 ,  H10N79/00

Abstract: An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

公开(公告)号：US20250006723A1

公开(公告)日：2025-01-02

申请号：US18225706

申请日：2023-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: H01L27/02 ,  H01L29/78

Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a substrate, a pickup region adjacent to one side of the first MOS transistor, and a protection diode adjacent to another side of the first MOS transistor. Preferably, the first MOS transistor includes a first gate structure on the substrate and a first source/drain region adjacent to two sides of the first gate structure, the protection diode is electrically connected to the first gate structure, and the pickup region and the protection diode include different conductive type.

公开(公告)号：US20250006634A1

公开(公告)日：2025-01-02

申请号：US18830609

申请日：2024-09-11

Applicant: United Microelectronics Corp.

Inventor： To-Wen Tsao ,  Ching-Chang Hsu

IPC: H01L23/528 ,  H01L23/522

Abstract: An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.