公开(公告)号：US20140177939A1

公开(公告)日：2014-06-26

申请号：US13721015

申请日：2012-12-20

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Chia-Chi Lo ,  Cheng-Hsiung Yang ,  Jun-Chung Hsu

IPC: G06T7/00

CPC classification number: H05K1/0269 ,  H05K3/0008 ,  H05K3/225 ,  H05K2201/09927 ,  H05K2201/09936

Abstract: Disclosed is a method of final defect inspection, including preparing a final defect inspection apparatus which includes a host device, a microscope, a bar code scanner, a support tool and a signal transceiver, using the host device to calibrate an original point in an outline of the circuit board based on a plurality of original mark positions generated by an electromagnetic pen, using the electromagnetic pen to mark each defect position on the inspection region on the circuit board where any defect is found through the microscope, using the signal transceiver to receive and transmit each defect position to the host device, and using the host device to calculate the coordinate of a scrap region based on a relative position between the original point and each defect position so as to generate a shipment file.

Abstract translation: 公开了一种最终缺陷检查的方法，包括使用主机设备准备包括主机，显微镜，条形码扫描仪，支持工具和信号收发器的最终缺陷检查设备来校准轮廓中的原始点 基于由电磁笔产生的多个原始标记位置的电路​​板，使用电磁笔来标记电路板上通过显微镜发现任何缺陷的检查区域上的每个缺陷位置，使用信号收发器接收 并且将每个缺陷位置发送到主机设备，并且使用主机设备基于原始点和每个缺陷位置之间的相对位置来计算废料区域的坐标，以便生成出货文件。

公开(公告)号：US20140116755A1

公开(公告)日：2014-05-01

申请号：US13663250

申请日：2012-10-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K3/4682 ,  H05K2201/09136 ,  H05K2201/2018

Abstract: A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping.

Abstract translation: 公开了一种层叠电路板结构，其包括第一电路金属层，第一绝缘层，至少一个第二电路金属层，至少一个第二绝缘层和支撑框架。 叠层电路板结构的总厚度小于150μm。 设置在由第一电路金属层和第一绝缘层形成的共面的外边缘处的支撑框架不覆盖第一电路金属层，并且由至少一种金属材料形成。 支撑框架为整个板结构提供物理支撑，而不影响电路连接，从而防止层压电路板结构翘曲。

公开(公告)号：US20140115888A1

公开(公告)日：2014-05-01

申请号：US13663333

申请日：2012-10-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K3/06

CPC classification number: H05K1/056 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0204 ,  H05K2201/029 ,  H05K2201/0323 ,  H05K2201/09054 ,  H05K2203/0323 ,  H05K2203/0384 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board.

Abstract translation: 一种制造芯片支撑板结构的方法，其包括以下步骤：形成金属基板结构，形成光致抗蚀剂图案，蚀刻金属基板结构以形成桨，去除光致抗蚀剂图案，将绝缘层压靠在桨上， 公开了抛光绝缘层，形成电路层和形成阻焊剂。 金属基板结构是通过将具有两个金属基底层的多层的阻挡层夹在中间而形成的。 在控制下将金属基底结构蚀刻到有效深度，使得如此形成的每个桨具有相同的形状和深度。 因此，本发明的方法可以广泛地应用于通常的批量生产过程，以有效地解决由于芯片支撑板中的深度差异，偏移，位置失配和剥离等现有技术的问题。

公开(公告)号：US20130219713A1

公开(公告)日：2013-08-29

申请号：US13663663

申请日：2012-10-30

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/24 ,  H05K3/4682 ,  H05K2201/0317 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49155

Abstract: A method of manufacturing a laminate circuit board with a multilayer circuit structure which includes the steps of forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer on the circuit metal layer, forming a cover layer to cover the substrate and the nanometer plating layer, forming through holes in the cover layer to generate openings exposing part of the nanometer plating layer, and finally forming a second metal layer on the cover layer to fill up the openings is disclosed. The nanometer plating layer is used to obtain same effect of previously roughening by chemical bonding, such that no circuit width is reserved for compensation, and the density of the circuit increases such that much more dense circuit can be implemented.

Abstract translation: 一种制造具有多层电路结构的叠层电路板的方法，包括以下步骤：在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成纳米电镀层，形成 盖层覆盖基板和纳米镀层，在盖层中形成孔，以产生露出纳米镀层的一部分的开口，最后在覆盖层上形成第二金属层以填充开口。 纳米电镀层用于通过化学键合获得与之前的粗糙化相同的效果，使得没有电路宽度被保留用于补偿，并且电路的密度增加，使得可以实现更加密集的电路。

公开(公告)号：US10779405B2

公开(公告)日：2020-09-15

申请号：US16045236

申请日：2018-07-25

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

公开(公告)号：US10440837B2

公开(公告)日：2019-10-08

申请号：US15864754

申请日：2018-01-08

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

公开(公告)号：US10383265B2

公开(公告)日：2019-08-13

申请号：US16115119

申请日：2018-08-28

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US20190160805A1

公开(公告)日：2019-05-30

申请号：US16199515

申请日：2018-11-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Shang-Chi WANG ,  Yun-Han YEH ,  Cyuan-Bang WU

IPC: B32B43/00

Abstract: A foil peeling apparatus adapted to a substrate having a foil thereon includes a foil peeling member, a connector and a controller. The foil peeling member has a foil peeling surface. The controller controls the connector to drive the peeling member to move along a path. The foil peeling surface of the peeling member in contact with, with an initial angle, the substrate, feeds toward the substrate for a first displacement, and then moves upwards and toward the substrate when the first feeding angle is decreased.

公开(公告)号：US20180332706A1

公开(公告)日：2018-11-15

申请号：US16045236

申请日：2018-07-25

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao LIN ,  Chiao-Cheng CHANG ,  Yi-Nong LIN

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42 ,  H05K3/18 ,  H05K3/10

Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

公开(公告)号：US20180303012A1

公开(公告)日：2018-10-18

申请号：US15859982

申请日：2018-01-02

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.