公开(公告)号：US09553590B1

公开(公告)日：2017-01-24

申请号：US13662795

申请日：2012-10-29

Applicant: Altera Corporation

Inventor： Valavan Manohararajah ,  David Lewis

IPC: H03K19/177 ,  H03K19/173 ,  G06F9/30 ,  G06F7/57 ,  G06F7/38 ,  G06F17/30 ,  G06F17/50

CPC classification number: H03K19/17708 ,  G06F9/30 ,  G06F17/30221 ,  G06F17/5027 ,  G06F17/5054 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of dedicated memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Programmably connectable direct interconnect between at least one respective individual one of the specialized processing blocks and at least one respective individual one of the dedicated memory modules allow the formation of a processor element from a specialized processing block and a memory module. The specialized processing block may be designed with a datapath and operators arranged to support the configuring of a processor element.

Abstract translation: 可编程集成电路器件包括多个可编程逻辑资源簇。 可编程设备互连资源允许可编程逻辑资源集群之间的用户定义的互连。 多个专用处理块具有专用算术运算器和可编程内部互连资源，并具有可编程地连接到可编程器件互连资源的输入和输出。 多个专用存储器模块具有可编程地连接到可编程器件互连资源的输入和输出。 专用处理块中的至少一个相应单独的一个可编程地可连接的直接互连和专用存储器模块中的至少一个相应的独立的一个允许从专门的处理块和存储器模块形成处理器元件。 专门的处理块可以被设计成具有数据路径和被配置为支持处理器元件的配置的操作者。

公开(公告)号：US09362913B1

公开(公告)日：2016-06-07

申请号：US14499006

申请日：2014-09-26

Applicant: Altera Corporation

Inventor： Herman Henry Schmit ,  David Lewis

IPC: H03K19/003 ,  H03K19/23 ,  H03K19/007 ,  G06F11/20

CPC classification number: H03K19/00392 ,  G06F7/501 ,  G06F11/187 ,  G06F11/2089 ,  G06F11/2094 ,  H03K19/00369 ,  H03K19/0075 ,  H03K19/23

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

Abstract translation: 诸如专用集成电路或可编程逻辑器件的集成电路可以包括多个配对电路的多个副本以及有时也被称为多模冗余的配置的多数投票电路。 加法器电路可以耦合到这些多个拷贝，并且基于从多个拷贝接收的信号产生进位信号和和信号。 加法器电路的进位信号可以提供多数投票操作的结果。 逻辑异或门可以在和信号和进位信号之间执行逻辑异或运算，从而产生误差信号。 错误信号可以指示多个副本之一产生与其他副本产生的输出不同的输出。

公开(公告)号：US09245085B2

公开(公告)日：2016-01-26

申请号：US14484655

申请日：2014-09-12

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50 ,  H03K19/177

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。

公开(公告)号：US09166570B2

公开(公告)日：2015-10-20

申请号：US13964901

申请日：2013-08-12

Applicant: Altera Corporation

Inventor： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC: H03K19/00 ,  H03K3/356 ,  H03K3/037 ,  H03K19/003 ,  H03K19/177

CPC classification number: H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract translation: 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：US20150134870A1

公开(公告)日：2015-05-14

申请号：US14075802

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。

公开(公告)号：US09024683B1

公开(公告)日：2015-05-05

申请号：US14022931

申请日：2013-09-10

Applicant: Altera Corporation

Inventor： David Lewis ,  Ryan Fung

IPC: H03K5/00

CPC classification number: H03K5/00 ,  G06F1/10 ,  G06F1/26 ,  H03K19/00346

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract translation: 时钟网络包括与第一多个时钟线相关联的第一多个屏蔽线和与第二多个时钟线相关联的第二多个屏蔽线。 时钟网络还包括与第一多个时钟线相关联的第一多个时钟活动程序电路和与第二多个时钟线相关联的第二多个时钟活动程序电路，其中第一和第二多个屏蔽线和 第一和第二多个时钟活动程序电路被配置为减少功率尖峰。

公开(公告)号：US20150052380A1

公开(公告)日：2015-02-19

申请号：US13966130

申请日：2013-08-13

Applicant: Altera Corporation

Inventor： David Lewis

IPC: G06F1/08

CPC classification number: G06F1/08 ,  G11C7/1075 ,  G11C7/222

Abstract: An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry.

Abstract translation: 提供了具有危险预测和预防电路的集成电路。 危险预测电路可以预测两个周期性信号之间的未来危险状况，并且危害预防电路可选择性地延迟两个周期性信号中的至少一个以避免预测的危险状况。 单端口存储器单元可以使用包括危险预测和防止电路的仲裁电路来提供多端口存储器功能，并且从至少两个请求发生器接收存储器访问请求。 仲裁电路可以在同步模式下操作，并且基于预定的逻辑表执行端口选择。 仲裁电路还可以以异步模式操作，并且一旦它被仲裁电路接收就执行存储器访问请求。 可以通过危险预测和预防电路来避免从至少两个请求发生器同时接收存储器访问请求而引起的转移性。

公开(公告)号：US20140331074A1

公开(公告)日：2014-11-06

申请号：US14332006

申请日：2014-07-15

Applicant: Altera Corporation

Inventor： David Lewis

IPC: G06F1/04 ,  G06F1/12

CPC classification number: G06F1/04 ,  G06F1/12 ,  G11C7/1075

Abstract: Integrated circuits having single-port memory elements may be provided. The single-port memory elements may be controlled using a control circuit to emulate multiport functionality. In one suitable embodiment, the control circuit may be an arbitration circuit configured to execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. In another suitable embodiment, the control circuit may be a sequencing circuit configured to service memory access requests from a synchronous port and an asynchronous port. Memory access requests received at the synchronous port may be serviced immediately, whereas memory access requests received at the asynchronous port may be synchronized to an internal memory clock signal and may be serviced after a preceding memory access request associated with the synchronous port has been serviced.

Abstract translation: 可以提供具有单端口存储元件的集成电路。 可以使用控制电路来控制单端口存储器元件来模拟多端口功能。 在一个合适的实施例中，控制电路可以是被配置为一旦被仲裁电路接收到就执行存储器请求的仲裁电路。 正在执行当前存储器访问时接收的请求可以被保持，直到当前存储器访问已经完成。 在另一个合适的实施例中，控制电路可以是被配置为从同步端口和异步端口服务存储器访问请求的排序电路。 在同步端口处接收到的存储器访问请求可以立即被服务，而在异步端口处接收的存储器访问请求可以被同步到内部存储器时钟信号，并且可以在与同步端口相关联的先前的存储器访问请求被服务之后进行服务。

公开(公告)号：US08878567B1

公开(公告)日：2014-11-04

申请号：US14062637

申请日：2013-10-24

Applicant: Altera Corporation

Inventor： James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy L. Lee ,  Rahul Saini ,  Henry Kim

IPC: H03K19/177 ,  H03K19/0175

CPC classification number: H03K19/17728 ,  G06F7/50 ,  H03K19/017581

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract translation: 公开了可以提供多个有利特征的逻辑元件（LE）。 例如，LE可以提供LUT和输入共享的高效灵活的使用。 LE还可以灵活地使用一个或多个专用加法器并且包括寄存器功能。

公开(公告)号：US08863059B1

公开(公告)日：2014-10-14

申请号：US13930018

申请日：2013-06-28

Applicant: Altera Corporation

Inventor： Ryan Fung ,  David Lewis ,  Valavan Manohararajah

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5059 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/17728 ,  H03K19/17736

Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括分析用户逻辑设计以识别用户逻辑设计内的路径的定时要求，确定沿着这些路径的等待时间要求，基于存储元件的可用性路由用户逻辑设计， 并入到这些路径中以满足等待时间要求，并且通过并入至少一些存储元件来重新定时跟踪该路由之后的用户逻辑设计。