公开(公告)号：US07932171B2

公开(公告)日：2011-04-26

申请号：US12357981

申请日：2009-01-22

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Margie T. Rios ,  Erwin Victor R. Cruz

IPC: H01L21/44

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05124

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract translation: 公开了一种用于形成螺柱凸起的半导体管芯的方法。 该方法包括在穿过毛细管中的孔的涂覆线的尖端处形成球，其中涂覆线具有芯和抗氧化涂层。 将形成的球按压到半导体管芯上的导电区域。 涂覆的线材被切割，从而在导电区域上留下导电柱状凸块，其中导电柱形凸块包括内部导电部分和外部抗氧化层。

公开(公告)号：US07682877B2

公开(公告)日：2010-03-23

申请号：US12118222

申请日：2008-05-09

Applicant: Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

Inventor： Rajeev Joshi ,  Jonathan A. Noquil ,  Consuelo N. Tangpuz

IPC: H01L21/00

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。

公开(公告)号：US20090130802A1

公开(公告)日：2009-05-21

申请号：US12358654

申请日：2009-01-23

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

公开(公告)号：US07504281B2

公开(公告)日：2009-03-17

申请号：US11180405

申请日：2005-07-12

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L21/00

CPC classification number: H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45147

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附接区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。

公开(公告)号：US20080036056A1

公开(公告)日：2008-02-14

申请号：US11693141

申请日：2007-03-29

Applicant: Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

Inventor： Rajeev Joshi ,  Consuelo Tangpuz ,  Romel Manatad

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US07256479B2

公开(公告)日：2007-08-14

申请号：US11035918

申请日：2005-01-13

Applicant: Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

Inventor： Jonathan A. Noquil ,  Connie Tangpuz ,  Romel Manatad ,  Stephen Martin ,  Rajeev Joshi ,  Venkat Iyer

IPC: H01L23/495

CPC classification number: H01L23/36 ,  H01L23/488 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K3/341 ,  H05K2201/09681 ,  H05K2201/10166 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract translation: 公开了一种半导体管芯封装。 它可以包括具有第一表面和第二表面的半导体管芯和引线框架结构。 模制材料可以围绕模具的至少一部分和引线框架结构的至少一部分形成。 可焊层可以在模制材料的外表面和半导体管芯的第一表面上。

公开(公告)号：US07215011B2

公开(公告)日：2007-05-08

申请号：US11213182

申请日：2005-08-25

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US06953998B2

公开(公告)日：2005-10-11

申请号：US10754095

申请日：2003-12-29

Applicant: Rajeev Joshi

Inventor： Rajeev Joshi

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/14 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/145 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/074 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the die serves as a drain connection while the solder balls serve as the source and gate connections.

Abstract translation: 不包括成型体或封装的半导体器件。 半导体器件包括衬底和耦合到衬底的管芯。 芯片耦合到衬底，使得假设MOSFET型器件的管芯的源极和栅极区域耦合到衬底。 焊球邻近管芯设置，使得当半导体器件耦合到印刷电路板时，裸片的暴露表面用作漏极连接，而焊球用作源极和栅极连接。

公开(公告)号：US06949410B2

公开(公告)日：2005-09-27

申请号：US10607633

申请日：2003-06-27

Applicant: Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

Inventor： Rajeev Joshi ,  Consuelo N. Tangpuz ,  Romel N. Manatad

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49562 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/49531 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract translation: 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。

公开(公告)号：US20050012225A1

公开(公告)日：2005-01-20

申请号：US10852732

申请日：2004-05-24

Applicant: Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

Inventor： Seung-Yong Choi ,  Min-Ho Park ,  Ji-Hwan Kim ,  Rajeev Joshi

IPC: H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L21/48 ,  H01L23/52

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/3512

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e.,interface) to the printed circuit board for any small die.

Abstract translation: 描述了包含导电粘合剂材料作为半导体管芯和图案化导电基板之间的电互连路线的封装半导体器件（晶片级芯片级封装）。 图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。 使用本发明允许形成较低价格的芯片级封装，其还克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。 因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。