公开(公告)号：US20220261351A1

公开(公告)日：2022-08-18

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20220124047A1

公开(公告)日：2022-04-21

申请号：US17566381

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L47/50 ,  H04L47/2475 ,  H04L47/24 ,  H04L49/90

Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

公开(公告)号：US20210165756A1

公开(公告)日：2021-06-03

申请号：US17153751

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Anil Vasudevan ,  David Harriman

IPC: G06F13/42 ,  G06F13/40

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

公开(公告)号：US10951525B2

公开(公告)日：2021-03-16

申请号：US16383591

申请日：2019-04-13

Applicant: Intel Corporation

Inventor： Anil Vasudevan

IPC: H04L12/56 ,  H04L12/743 ,  H04L12/725 ,  H04L29/06 ,  H04L12/741

Abstract: Some examples provide for storage of context information in memory in the process of creating a network connection and subsequent availability of the context information. A context address can refer to context for a packet processing path. A host can provide a context address and associated packet characteristics to a network interface device. If the network interface device receives a packet with the characteristics, the context address can be passed to the host and the host can retrieve the context information using the context address.

公开(公告)号：US20210049102A1

公开(公告)日：2021-02-18

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20190303303A1

公开(公告)日：2019-10-03

申请号：US15940719

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Venkata Krishnan ,  Lawrence Stewart ,  Anil Vasudevan ,  Ren Wang

IPC: G06F12/123 ,  G06F12/122 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0811

Abstract: A method for detecting repetitive data accesses and automatically storing the data into the local cache, the method including: storing a cache line in a first cache of a first processor; tracking accesses to the cache line by monitoring executions of a snapshot instruction made by a second processor; and controlling enablement of a load operation based on the tracked accesses. The load operation is performed by storing a copy of the cache line into a local cache of the second processor and changing the cache coherence state of the cache line in the first cache to a shared state.

公开(公告)号：US10158585B2

公开(公告)日：2018-12-18

申请号：US13773255

申请日：2013-02-21

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L12/861 ,  G06F9/48 ,  G06F9/52 ,  G06F9/32 ,  H04L12/879 ,  G06F9/448

Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US10142231B2

公开(公告)日：2018-11-27

申请号：US15087527

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Anil Vasudevan

IPC: H04L12/747 ,  H04L12/743 ,  H04L12/873 ,  G06F13/40

Abstract: Technologies for accelerating non-uniform network input/output accesses include a multi-home network interface controller (NIC) of a network computing device communicatively coupled to a plurality of non-uniform memory access (NUMA) nodes, each of which include an allocated number of processor cores of a physical processor package and an allocated portion of a main memory directly linked to the physical processor package. The multi-home NIC includes a logical switch communicatively coupled to a plurality of logical NICs, each of which is communicatively coupled to a corresponding NUMA node. The multi-home NIC is configured to facilitate the ingress and egress of network packets by determining a logical path for each network packet received at the multi-home NIC based on a relationship between one of the NUMA nodes and/or a logical NIC (e.g., to forward the network packet from the multi-home NIC) coupled to the one of the NUMA nodes. Other embodiments are described herein.

公开(公告)号：US20180159803A1

公开(公告)日：2018-06-07

申请号：US15832195

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Y. Tsao ,  Anil Vasudevan

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/863

CPC classification number: H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

公开(公告)号：US20160321203A1

公开(公告)日：2016-11-03

申请号：US15008083

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Yadong Li ,  Linden Cornett ,  Manasi Deval ,  Anil Vasudevan ,  Parthasarathy Sarangam

IPC: G06F13/24 ,  H04L29/06

CPC classification number: G06F13/24 ,  H04L69/165

Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.