公开(公告)号：US11728265B2

公开(公告)日：2023-08-15

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian ,  Dilan Seneviratne ,  Yonggang Li ,  Sameer Paital ,  Darko Grujicic ,  Rengarajan Shanmugam ,  Melissa Wette ,  Srinivas Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L27/01 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/4846 ,  H01L21/76871 ,  H01L23/498 ,  H01L23/5226 ,  H01L23/647 ,  H01L24/09 ,  H01L27/016 ,  H01L28/24

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US11728077B2

公开(公告)日：2023-08-15

申请号：US17482861

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

CPC classification number: H01F1/20 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/2804 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01F2027/2809 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US20230076917A1

公开(公告)日：2023-03-09

申请号：US17470684

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Brandon C. Marin ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Jeremy D. Ecton ,  Hari Mahalingam ,  Benjamin Duong

IPC: G02F1/035

Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

公开(公告)号：US20220093316A1

公开(公告)日：2022-03-24

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01L23/64 ,  H01F41/32 ,  H01L23/498

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20210273036A1

公开(公告)日：2021-09-02

申请号：US16804317

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Prithwish Chatterjee ,  Haifa Hariri ,  Yikang Deng ,  Sheng C. Li ,  Srinivas Pietambaram

IPC: H01L49/02 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

公开(公告)号：US20250112175A1

公开(公告)日：2025-04-03

申请号：US18477638

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jesse C. Jones ,  Yosef Kornbluth ,  Mitchell Page ,  Soham Agarwal ,  Fanyi Zhu ,  Shuren Qu ,  Hanyu Song ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Bai Nie ,  Nicholas Haehn ,  Astitva Tripathi ,  Mohamed R. Saber ,  Sheng Li ,  Pratyush Mishra ,  Benjamin T. Duong ,  Kari Hernandez ,  Praveen Sreeramagiri ,  Yi Li ,  Ibrahim El Khatib ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Haobo Chen ,  Robin Shea McRee ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L25/065

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

公开(公告)号：US12255130B2

公开(公告)日：2025-03-18

申请号：US16884452

申请日：2020-05-27

Applicant: INTEL CORPORATION

Inventor： Hongxia Feng ,  Jeremy Ecton ,  Aleksandar Aleksov ,  Haobo Chen ,  Xiaoying Guo ,  Brandon C. Marin ,  Zhiguo Qian ,  Daryl Purcell ,  Leonel Arana ,  Matthew Tingey

IPC: H01L23/522 ,  H01L23/66

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US20240213170A1

公开(公告)日：2024-06-27

申请号：US18086293

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

公开(公告)号：US20240128247A1

公开(公告)日：2024-04-18

申请号：US18046635

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC: H01L25/16 ,  H01F27/02 ,  H01F27/28 ,  H01F27/29 ,  H01F41/00 ,  H01F41/04 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01F27/022 ,  H01F27/2804 ,  H01F27/292 ,  H01F41/005 ,  H01F41/041 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16235 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.