中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

304 records (took 0.032 seconds)

    MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATION
    51.
    发明申请
    MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATION 有权
    通过封装延长连接器上的胶管的微电子组件

    公开(公告)号：US20150014856A1

    公开(公告)日：2015-01-15

    申请号：US13942602

    申请日：2013-07-15

    Applicant: Invensas Corporation

    Inventor： Ilyas Mohammed ,  Belgacem Haba

    IPC: H01L23/28 ,  H01L21/56

    CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.

    Abstract translation: 微电子组件或封装可以包括第一和第二支撑元件以及在支撑元件的向内表面之间的微电子元件。 第一连接器和第二连接器，例如焊球，金属柱，螺柱凸起等从相应的支撑元件向内表面并且彼此对齐并且彼此电连接。 电介质增强套环设置在第一连接器，第二连接器或两者的外表面上，并且封装将成对的耦合连接器彼此分开并且可以填充支撑元件之间的空间。

    Co-support module and microelectronic assembly
    54.
    发明授权
    Co-support module and microelectronic assembly 有权
    共同支持模块和微电子组装

    公开(公告)号：US08848392B2

    公开(公告)日：2014-09-30

    申请号：US13840542

    申请日：2013-03-15

    Applicant: Invensas Corporation

    Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

    IPC: H05K1/11 ,  H05K1/14 ,  B81B7/00

    CPC classification number: B81B7/007 ,  H01L23/5384 ,  H01L25/0652 ,  H01L2224/12105 ,  H01L2224/20

    Abstract: A module is configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module includes a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts include first contacts having address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.

    Abstract translation: 模块被配置为与具有端子和微电子元件的微电子组件连接。 该模块包括电路板承载导体，其被配置为承载命令和地址信息，共同支撑联接到导体的触点以及耦合到导体的模块触点。 共同支持触点包括具有以与第一类型的微电子组件连接的第一预定布置布置的地址和命令信息分配的第一触点，其中微电子元件被配置为通过第一触点对其耦合到其上的命令和地址信息进行采样 以及用于与第二类型的微电子组件连接的第二预定布置，其中微电子元件被配置为以大于第二采样率的第一采样率对第一触点的子集进行采样以对其进行采样，从而对与其耦合的命令和地址信息进行采样 第一个采样率。

    Reconfigurable pop
    55.
    发明授权
    Reconfigurable pop 有权
    可重新配置的流行音乐

    公开(公告)号：US08786069B1

    公开(公告)日：2014-07-22

    申请号：US13898952

    申请日：2013-05-21

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

    IPC: H01L23/498 ,  H01L23/522 ,  H01L25/065

    CPC classification number: H01L23/49811 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A microelectronic package can include lower and upper package faces, lower terminals at the lower package face configured for connection with a first component, upper terminals at the upper package face configured for connection with a second component, first and second microelectronic elements each having memory storage array function, and conductive interconnects each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects can include first conductive interconnects configured to carry address information, signal assignments of a first set of the first interconnects having 180° rotational symmetry about a theoretical rotational axis with signal assignments of a second set of first interconnects. The conductive interconnects can also include second conductive interconnects configured to carry data information, the position of each second conductive interconnect having 180° rotational symmetry about the rotational axis with a position of a corresponding no-connect conductive interconnect.

    Abstract translation: 微电子封装可以包括下封装面和上封装面，下封装面处的下端子被配置为与第一部件连接，上封装面上的上端子被配置为与第二元件连接，第一和第二微电子元件各自具有存储器 阵列功能和导电互连，每个电连接至少一个下端子与至少一个上端子。 导电互连可以包括被配置为承载地址信息的第一导电互连，具有关于第二组第一互连的信号分配的理论旋转轴线具有180°旋转对称性的第一组互连的第一组的信号分配。 导电互连还可以包括被配置为承载数据信息的第二导电互连，每个第二导电互连的位置具有相对于不连接导电互连的位置的围绕旋转轴线的180°旋转对称。

    Symbiotic Network On Layers
    60.
    发明申请
    Symbiotic Network On Layers 有权

    公开(公告)号：US20220150184A1

    公开(公告)日：2022-05-12

    申请号：US17583872

    申请日：2022-01-25

    Applicant: Invensas Corporation

    Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

    IPC: H04L49/109

    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Patent Agency Ranking