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    Network On Layer Enabled Architectures
    1.
    发明申请
    Network On Layer Enabled Architectures 有权

    公开(公告)号：US20220139883A1

    公开(公告)日：2022-05-05

    申请号：US17577944

    申请日：2022-01-18

    Applicant: Invensas Corporation

    Inventor： Javier A. DeLaCruz ,  Belgacem Haba

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F15/78 ,  H01L23/532

    Abstract: The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.

    3D MEMORY CIRCUIT
    2.
    发明申请
    3D MEMORY CIRCUIT 有权

    公开(公告)号：US20210149586A1

    公开(公告)日：2021-05-20

    申请号：US17098299

    申请日：2020-11-13

    Applicant: Invensas Corporation

    Inventor： Javier A. DeLaCruz ,  David E. Fisch

    IPC: G06F3/06

    Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.

    Symbiotic Network On Layers
    3.
    发明申请
    Symbiotic Network On Layers 有权

    公开(公告)号：US20220150184A1

    公开(公告)日：2022-05-12

    申请号：US17583872

    申请日：2022-01-25

    Applicant: Invensas Corporation

    Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

    IPC: H04L49/109

    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

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