公开(公告)号：US20120079215A1

公开(公告)日：2012-03-29

申请号：US13307492

申请日：2011-11-30

Applicant: Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

Inventor： Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：US08095824B2

公开(公告)日：2012-01-10

申请号：US12638181

申请日：2009-12-15

Applicant: Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

Inventor： Jan Gray ,  Martin Taillefer ,  Yossi Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Vinod Grover ,  Mike Magruder ,  Matt Tolton ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin

IPC: G06F11/00

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：US08073673B2

公开(公告)日：2011-12-06

申请号：US12104274

申请日：2008-04-16

Applicant: Alan G. Bishop ,  Martin Taillefer ,  Landon M Dyer

Inventor： Alan G. Bishop ,  Martin Taillefer ,  Landon M Dyer

IPC: G06F9/455

CPC classification number: G06F12/1009

Abstract: A first software program executing on a computing device emulates a second computing device executing a software program using emulated memory. The first software program permits the second software program to perform an operation on a contiguous portion of the emulated memory only when a pointer and a table entry both contain the same identifier, thus protecting against common types of memory usage errors in the second software program. The pointer has an address to the contiguous portion. The table entry maps to the contiguous portion. A plurality of table entries map to a respective plurality of contiguous portion of the emulated memory. A plurality of the pointers each contain the address to a respective contiguous portion of the emulated memory as well as containing an identifier corresponding to the respective contiguous portion of the emulated memory. The second computing device can be high or low in resources.

Abstract translation: 在计算设备上执行的第一软件程序模拟使用模拟存储器来执行软件程序的第二计算设备。 第一软件程序允许第二软件程序仅在指针和表条目都包含相同的标识符时才对仿真存储器的连续部分执行操作，从而防止在第二软件程序中的常见类型的存储器使用错误。 指针具有连续部分的地址。 表条目映射到连续部分。 多个表条目映射到仿真存储器的相应多个连续部分。 多个指针各自包含地址给仿真存储器的相应连续部分，并且包含对应于仿真存储器的相应连续部分的标识符。 第二计算设备可以是高或低的资源。

公开(公告)号：US20110145552A1

公开(公告)日：2011-06-16

申请号：US12638064

申请日：2009-12-15

Applicant: Koichi Yamada ,  Gad Sheaffer ,  Jan Gray ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  Ali-Reza Adl-Tabatabai ,  David Callahan

Inventor： Koichi Yamada ,  Gad Sheaffer ,  Jan Gray ,  Landy Wang ,  Martin Taillefer ,  Arun Kishan ,  Ali-Reza Adl-Tabatabai ,  David Callahan

IPC: G06F9/312

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在执行无界事务存储器（UTM）事务期间经由用户线程的环转移以内核模式接收控制的方法，更新与相关联的事务状态寄存器（TSR）相关联的事务状态寄存器（TSR）的状态 用户线程和用户线程的上下文存储TSR，然后在从内核模式到用户线程的转换期间恢复上下文。 以这种方式，UTM事务可以继续恢复用户线程。 描述和要求保护其他实施例。

公开(公告)号：US20110145498A1

公开(公告)日：2011-06-16

申请号：US12638345

申请日：2009-12-15

Applicant: Martin Taillefer ,  Jan Gray ,  Richard Wurdack ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai

Inventor： Martin Taillefer ,  Jan Gray ,  Richard Wurdack ,  Gad Sheaffer ,  Ali-Reza Adl-Tabatabai

IPC: G06F12/08

CPC classification number: G06F9/467 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88 ,  G06F2201/885

Abstract: Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.

Abstract translation: 监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。 所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。 所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

公开(公告)号：US07941411B2

公开(公告)日：2011-05-10

申请号：US11824379

申请日：2007-06-29

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F7/00 ,  G06F17/00

CPC classification number: G06F9/466

Abstract: Various technologies and techniques are described for providing a transaction grouping feature for use in programs operating under a transactional memory system. The transaction grouping feature is operable to allow transaction groups to be created that contain related transactions. The transaction groups are used to enhance performance and/or operation of the programs. Different locking and versioning mechanisms can be used with different transaction groups. When running transactions, a hardware transactional memory execution mechanism can be used for one transaction group while a software transactional memory execution mechanism used for another transaction group.

Abstract translation: 描述了用于提供用于在事务存储器系统下操作的程序中的事务分组特征的各种技术和技术。 事务分组功能可操作以允许创建包含相关事务的事务组。 交易组用于增强程序的性能和/或操作。 不同的锁定和版本控制机制可以与不同的事务组一起使用。 运行事务时，硬件事务内存执行机制可用于一个事务组，而另一个事务组则使用软件事务内存执行机制。

公开(公告)号：US20100332808A1

公开(公告)日：2010-12-30

申请号：US12493168

申请日：2009-06-26

Applicant: Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

Inventor： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

IPC: G06F9/30 ,  G06F9/312

CPC classification number: G06F9/3004 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3857 ,  G06F9/467

Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

Abstract translation: 最大限度地减少无界事务内存系统中的代码重复。 一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作 与未来的TM实现可能会引入未知的未来TM执行模式。

公开(公告)号：US07725305B2

公开(公告)日：2010-05-25

申请号：US11450233

申请日：2006-06-08

Applicant: Martin Taillefer ,  Bruno Silva ,  Stanley W. Adermann ,  Landon M. Dyer

Inventor： Martin Taillefer ,  Bruno Silva ,  Stanley W. Adermann ,  Landon M. Dyer

IPC: G06F9/455

CPC classification number: G06F9/45537

Abstract: A computing device hosts a virtual machine executing a guest that issues guest hardware requests by way of any of a plurality of paths. Such paths include a path to non-existent virtual hardware, where an emulator intercepts and processes such guest hardware request with a corresponding actual hardware command; a path to an instantiated operating system, where the instantiated operating system processes each such guest hardware request with a corresponding actual hardware request; and a path to device hardware, where the device hardware directly processes each such guest hardware request.

Abstract translation: 计算设备承载执行客户机的虚拟机，其通过多条路径中的任何路径发出客户机硬件请求。 这样的路径包括到不存在的虚拟硬件的路径，其中仿真器使用相应的实际硬件命令拦截并处理这样的访客硬件请求; 实例化操作系统的路径，其中实例操作系统用相应的实际硬件请求处理每个这样的客户硬件请求; 以及设备硬件的路径，其中设备硬件直接处理每个这样的客户机硬件请求。

公开(公告)号：US20090007107A1

公开(公告)日：2009-01-01

申请号：US11823212

申请日：2007-06-27

Applicant: Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

Inventor： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F9/45533

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

Abstract translation: 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US07434025B2

公开(公告)日：2008-10-07

申请号：US11489079

申请日：2006-07-18

Applicant: Martin Taillefer

Inventor： Martin Taillefer

IPC: G06F12/00

CPC classification number: G06F12/1009 ,  G06F12/109

Abstract: Guest logical to physical translation is leveraged for host-side memory access. A contiguous portion of host physical address space is dedicated to the guest operating system. A reusable offset value may be calculated upon guest operating system initialization. Everything stored in the guest “physical” address space can be directly mapped to the contiguous portion of host physical address space using the reusable offset value, if necessary, thereby greatly reducing mapping complexity for both store and look-up operations.

Abstract translation: 客户逻辑的物理翻译是利用主机端内存访问。 主机物理地址空间的连续部分专用于客户机操作系统。 可以在客户操作系统初始化时计算可重用的偏移值。 如果需要，存储在访客“物理”地址空间中的所有内容都可以使用可重用的偏移值直接映射到主机物理地址空间的连续部分，从而大大降低了存储和查找操作的映射复杂度。